公开(公告)号：US20170373038A1

公开(公告)日：2017-12-28

申请号：US15696247

申请日：2017-09-06

申请人： MediaTek Inc.

发明人： Tzu-Hung LIN ,  Ching-Wen HSIAO ,  I-Hsuan PENG

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L25/16 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L21/60

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2021/60015 ,  H01L2021/60232 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/10156 ,  H01L2224/11 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/73267 ,  H01L2224/81 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00012

摘要： A semiconductor package structure has a first electronic component on an insulating layer, a dielectric layer on the insulating layer and surrounding the first electronic component, a second electronic component stacked on the first electronic component, wherein an active surface of the first electronic component faces an active surface of the second electronic component, a molding compound on the first electronic component and surrounding the second electronic component, a third electronic component stacked on the second electronic component and the molding compound.

公开(公告)号：US20170186676A1

公开(公告)日：2017-06-29

申请号：US15460583

申请日：2017-03-16

申请人： MEDIATEK, INC.

发明人： Wen-Sung HSU ,  Tzu-Hung LIN ,  Ta-Jen YU

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/49811 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate having a die attach surface. A conductive trace is disposed on the substrate, wherein the conductive trace is elongated and carries a signal or a ground across at least a portion of the substrate. A die is mounted on the die attach surface of the substrate via a conductive pillar bump, the conductive pillar bump being rounded and elongated such that the conductive pillar bump extends along a length of the conductive trace and contacts the conductive trace at an end or at an intermediate portion thereof. The die further includes a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, and wherein the first edge is not adjacent to the second edge.

公开(公告)号：US20170098629A1

公开(公告)日：2017-04-06

申请号：US15218379

申请日：2016-07-25

申请人： MediaTek Inc.

发明人： Nai-Wei LIU ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO ,  Wei-Che HUANG

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L23/3114 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/19011 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2224/83

摘要： A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.

公开(公告)号：US20170098589A1

公开(公告)日：2017-04-06

申请号：US15212113

申请日：2016-07-15

申请人： MediaTek Inc.

发明人： Nai-Wei LIU ,  Tzu-Hung LIN ,  I-Hsuan PENG ,  Ching-Wen HSIAO ,  Wei-Che HUANG

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L21/568 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/29016 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/37001

摘要： A semiconductor package structure is provided. The structure includes a molding compound having a dicing lane region. A semiconductor die is disposed in the molding compound and surrounded by the dicing lane region. The semiconductor die has a first surface and a second surface opposite thereto, and the first and second surfaces are exposed from the molding compound. The structure further includes a redistribution layer (RDL) structure disposed on the first surface of the semiconductor die and covering the molding compound. The RDL structure includes a photo-sensitive material and has an opening aligned with the dicing lane region.

公开(公告)号：US20160268234A1

公开(公告)日：2016-09-15

申请号：US15014604

申请日：2016-02-03

申请人： MediaTek Inc.

发明人： Tzu-Hung LIN ,  Ching-Wen HSIAO ,  I-Hsuan PENG

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32265 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/92133 ,  H01L2225/06513 ,  H01L2225/06558 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/014

摘要： The invention provides a semiconductor package assembly. The semiconductor package assembly includes a semiconductor die. A first molding compound covers a back surface of the semiconductor die. A redistribution layer (RDL) structure is disposed on a front surface of the semiconductor die. The semiconductor die is coupled to the RDL structure. A second molding compound is disposed on the front surface of the semiconductor die and embedded in the RDL structure. A passive device is disposed on the second molding compound and coupled to the semiconductor die.

摘要翻译： 本发明提供一种半导体封装组件。 半导体封装组件包括半导体管芯。 第一模塑料覆盖半导体管芯的背面。 再分布层（RDL）结构设置在半导体管芯的前表面上。 半导体管芯耦合到RDL结构。 第二模塑料被设置在半导体管芯的前表面并嵌入RDL结构中。 无源器件设置在第二模塑料上并与半导体管芯耦合。

公开(公告)号：US20160211194A1

公开(公告)日：2016-07-21

申请号：US14601440

申请日：2015-01-21

申请人： MediaTek Inc.

发明人： Cheng-Chou HUNG ,  Ming-Tzong YANG ,  Tung-Hsing LEE ,  Wei-Che HUANG ,  Yu-Hua HUANG ,  Tzu-Hung LIN

IPC分类号： H01L23/48 ,  H01L21/761 ,  H01L21/768 ,  H01L29/06

CPC分类号： H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor package structure and method for forming the same are provided. The semiconductor package structure includes a substrate and the substrate has a front side and a back side. The semiconductor package structure includes a through silicon via (TSV) interconnect structure formed in the substrate; and a first guard ring doped region and a second guard ring doped region formed in the substrate, and the first guard ring doped region and the second guard ring doped region are adjacent to the TSV interconnect structure.

摘要翻译： 提供一种半导体封装结构及其形成方法。 半导体封装结构包括衬底，并且衬底具有正面和背面。 半导体封装结构包括在衬底中形成的穿硅通孔（TSV）互连结构; 以及形成在所述衬底中的第一保护环掺杂区域和第二保护环掺杂区域，并且所述第一保护环掺杂区域和所述第二保护环掺杂区域与所述TSV互连结构相邻。

公开(公告)号：US20160111358A1

公开(公告)日：2016-04-21

申请号：US14980445

申请日：2015-12-28

申请人： MediaTek Inc.

发明人： Wen-Sung HSU ,  Tzu-Hung LIN ,  Ta-Jen YU

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49811 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. First and second conductive traces are disposed on the substrate. A conductive pillar bump is disposed on the second conductive trace, and a first conductive structure is disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate. A semiconductor die is disposed over the first conductive trace, wherein the conductive pillar bump connects to the semiconductor die.

摘要翻译： 提供半导体封装。 在一种配置中，半导体封装包括衬底。 第一和第二导电迹线设置在基板上。 导电柱突起设置在第二导电迹线上，并且第一导电结构设置在第二导电迹线和导电柱突起之间或第二导电迹线和基底之间。 半导体管芯设置在第一导电迹线上，其中导电柱凸块连接到半导体管芯。

公开(公告)号：US20160099231A1

公开(公告)日：2016-04-07

申请号：US14741820

申请日：2015-06-17

申请人： MediaTek Inc.

发明人： Ming-Tzong YANG ,  Wei-Che HUANG ,  Tzu-Hung LIN

IPC分类号： H01L25/065 ,  H01L23/522 ,  H01L23/31 ,  H01L23/492 ,  H01L23/495

CPC分类号： H01L23/5226 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/18161 ,  H01L2924/18162

摘要： The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package and a second semiconductor package stacked on the first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure. A first semiconductor die is coupled to the first RDL structure. A first molding compound surrounds the first semiconductor die, and is in contact with the RDL structure and the first semiconductor die. The second semiconductor package includes a second redistribution layer (RDL) structure. A first dynamic random access memory (DRAM) die without through silicon via (TSV) interconnects formed passing therethrough is coupled to the second RDL structure.

摘要翻译： 本发明提供一种半导体封装组件。 半导体封装组件包括堆叠在第一半导体封装上的第一半导体封装和第二半导体封装。 第一半导体封装包括第一再分配层（RDL）结构。 第一半导体裸片耦合到第一RDL结构。 第一模塑料围绕第一半导体管芯，并与RDL结构和第一半导体管芯接触。 第二半导体封装包括第二再分配层（RDL）结构。 通过其形成的通过硅通孔（TSV）互连的第一动态随机存取存储器（DRAM）管芯被耦合到第二RDL结构。

公开(公告)号：US20150194403A1

公开(公告)日：2015-07-09

申请号：US14663755

申请日：2015-03-20

申请人： MediaTek Inc

发明人： Kuei-Ti CHAN ,  Tzu-Hung LIN ,  Ching-Liou HUANG

IPC分类号： H01L23/00 ,  H01L23/528 ,  H01L23/31 ,  H01L23/64 ,  H01L23/66

CPC分类号： H01L23/528 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/6677 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12 ,  H01L2924/1206 ,  H01Q23/00 ,  H01L2224/05552

摘要： A semiconductor package includes a substrate, a first passivation layer disposed on the substrate, and an under bump metallurgy layer disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer, and an additional under bump metallurgy layer is disposed on the first passivation layer, isolated from the under bump metallurgy layer. A conductive pillar is disposed on the additional under bump metallurgy layer, wherein the conductive pillar and the passive device are at the same level.

摘要翻译： 半导体封装包括衬底，设置在衬底上的第一钝化层和设置在第一钝化层上的凸块下金属层。 无源器件设置在凸块下金属层上，并且附加的凸块下金属层设置在与凸块下金属层隔离的第一钝化层上。 导电柱设置在另外的凸块下金属层上，其中导电柱和无源器件处于同一水平。

公开(公告)号：US20150115406A1

公开(公告)日：2015-04-30

申请号：US14284199

申请日：2014-05-21

申请人： MediaTek Inc.

发明人： Tzu-Hung LIN ,  Cheng-Chou HUNG

IPC分类号： H01L49/02

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L23/53238 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2223/6677 ,  H01L2224/02181 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08123 ,  H01L2224/08265 ,  H01L2224/11019 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/85007 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19051 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014

摘要： The invention provides a semiconductor structure. The semiconductor structure includes a substrate. A first passivation layer is disposed on the substrate. A conductive pad is disposed on the first passivation layer. A second passivation layer is disposed on the first passivation layer. A passive device is disposed on the conductive pad, passing through the second passivation layer. An organic solderability preservative film covers the passive device.

摘要翻译： 本发明提供一种半导体结构。 半导体结构包括基板。 第一钝化层设置在基板上。 导电焊盘设置在第一钝化层上。 第二钝化层设置在第一钝化层上。 无源器件设置在导电焊盘上，穿过第二钝化层。 有机可焊性防腐膜覆盖无源器件。