公开(公告)号：US20250006518A1

公开(公告)日：2025-01-02

申请号：US18753006

申请日：2024-06-25

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Wei LEI ,  Yu LEI ,  Ju Hyun OH ,  Zhimin QI ,  Sahil Jaykumar PATEL ,  Yi XU ,  Aixi ZHANG ,  Bingqian LIU ,  Cong TRINH ,  Xianmin TANG ,  Hayrensa ABLAT

IPC: H01L21/67 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532

Abstract: Embodiments herein relate to a method, semiconductor device structures, and multi-chamber processing system for exposing a semiconductor device structure to an oxidizing plasma to form an oxide layer on at least one electrical connection formed in at least one feature formed within a dielectric layer of the semiconductor device structure, performing an etch process to remove the oxide layer and form an etch recess between a portion of the electrical connection and the dielectric layer At least a portion of the etch recess extends underneath at least a portion of the dielectric layer, and filling the at least one feature and the etch recess with a metal material.

公开(公告)号：US20240355673A1

公开(公告)日：2024-10-24

申请号：US18136970

申请日：2023-04-20

Applicant: Applied Materials, Inc.

Inventor： Wei LEI ,  Sahil PATEL ,  Yixiong YANG ,  Yu LEI ,  Shiyu YUE ,  Yi XU ,  Tuerxun AILIHUMAER ,  Juhyun OH ,  Xianmin TANG ,  Rongjun WANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  C23C14/18 ,  H01L21/02063 ,  H01L21/28568

Abstract: Semiconductor devices and methods for molybdenum fill in semiconductor devices are provided. In one aspect, a method for processing a semiconductor device substrate is provided. The method includes exposing at least one feature formed in a dielectric layer to a grain modification layer deposition process to deposit a grain modification layer over at least a portion of the at least one feature. The at least one feature is defined by sidewall surfaces formed in the dielectric layer and a bottom surface extending between the sidewall surfaces. The method further includes exposing the at least one feature to a molybdenum deposition process to form a molybdenum-fill layer on the grain modification layer, wherein the grain modification layer comprises a metal different from molybdenum.

公开(公告)号：US20240145300A1

公开(公告)日：2024-05-02

申请号：US17977411

申请日：2022-10-31

Applicant: Applied Materials, Inc.

Inventor： Sahil PATEL ,  Wei LEI ,  Xingyao GAO ,  Shirish A. PETHE ,  Yu LEI

IPC: H01L21/768 ,  H01L21/3205 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/76841 ,  H01L21/32051 ,  H01L21/67017 ,  H01L21/67706

Abstract: Methods and apparatus for processing a substrate are provided. In some embodiments, a method includes: depositing a metal buffer layer on a substrate and within a feature disposed in a dielectric layer of the substrate. The buffer layer is deposited using a first physical vapor deposition (PVD) process at a chamber pressure of less than 500 mTorr while applying less than or equal to 0.08 watts/cm2 of RF bias power to the substrate if the chamber pressure is less than or equal to 3 mTorr and applying less than or equal to 0.8 watts/cm2 of RF bias power to the substrate if the chamber pressure is greater than 3 mTorr. A metal liner layer is deposited atop the buffer layer using a second PVD process at a chamber pressure of less than or equal to 3 mTorr while applying greater than 0.08 watts/cm2 of RF bias power to the substrate.

公开(公告)号：US20240006236A1

公开(公告)日：2024-01-04

申请号：US18133065

申请日：2023-04-11

Applicant: Applied Materials, Inc.

Inventor： Tsung-Han YANG ,  Junyeong YUN ,  Rongjun WANG ,  Yi XU ,  Yu LEI ,  Wenting HOU ,  Xianmin TANG

IPC: H01L21/768 ,  H01J37/32

CPC classification number: H01L21/76876 ,  H01J37/321 ,  H01L21/76843 ,  H01L21/76895 ,  H01J2237/338 ,  H01J37/32899

Abstract: A method of forming a structure on a substrate includes forming a tungsten nucleation layer within at least one feature. The method includes forming the nucleation layer via a cyclic vapor deposition process. The cyclic vapor deposition process includes forming a portion of the nucleation layer and then exposing the exposing the nucleation layer a chemical vapor transport (CVT) process to remove impurities from the portion of the nucleation layer. The CVT process may be performed at a temperature of 400 degrees Celsius or less and comprises forming a plasma from a processing gas comprising greater than or equal to 90% of hydrogen gas of a total flow of hydrogen gas and oxygen.

公开(公告)号：US20210343508A1

公开(公告)日：2021-11-04

申请号：US16863541

申请日：2020-04-30

Applicant: APPLIED MATERIALS, INC.

Inventor： Andrew NGUYEN ,  Xue Yang CHANG ,  Yu LEI ,  Xianmin TANG ,  John C. FORSTER ,  Yogananda Sarode VISHWANATH ,  Abilash SAINATH ,  Tza-Jing GUNG

IPC: H01J37/32 ,  C23C16/44

Abstract: Embodiments of process kits for use in a process chamber are provided herein. In some embodiments, a process kit for use in a process chamber includes: a chamber liner having a tubular body with an upper portion and a lower portion; a confinement plate coupled to the lower portion of the chamber liner and extending radially inward from the chamber liner, wherein the confinement plate includes a plurality of slots; a shield ring disposed within the chamber liner and movable between the upper portion of the chamber liner and the lower portion of the chamber liner; and a plurality of ground straps coupled to the shield ring at a first end of each ground strap of the plurality of ground straps and to the confinement plate at a second end of each ground strap to maintain electrical connection between the shield ring and the chamber liner when the shield ring moves.

公开(公告)号：US20210320034A1

公开(公告)日：2021-10-14

申请号：US16845749

申请日：2020-04-10

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei LEI ,  Yi XU ,  Yu LEI ,  Tae Hong HA ,  Raymond HUNG ,  Shirish A. PETHE

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/3213

Abstract: Methods and apparatus for selectively depositing a tungsten layer atop a dielectric surface. In embodiments the method includes: depositing a tungsten layer via a physical vapor deposition (PVD) process atop a substrate field and atop a sidewall and a dielectric bottom surface of a feature disposed in a substrate to form a first tungsten portion having a first thickness atop the substrate field, a second tungsten portion having a second thickness atop the sidewall, and a third tungsten portion having a third thickness atop the dielectric bottom surface, wherein the second thickness is less than the first thickness and third thickness; oxidizing a top surface of the tungsten layer to form a first oxidized tungsten portion atop the substrate field, a second oxidized tungsten portion atop the side wall, and a third oxidized tungsten portion atop the dielectric bottom surface; removing the first oxidized tungsten portion, the second oxidized tungsten portion and the third oxidized tungsten portion, wherein the second tungsten portion is completely removed from the sidewall; and passivating or completely removing the first tungsten portion from the substrate field.

公开(公告)号：US20190157145A1

公开(公告)日：2019-05-23

申请号：US16252100

申请日：2019-01-18

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Feiyue MA ,  Yu LEI ,  Kai WU ,  Mehul B. NAIK ,  Zhiyuan WU ,  Vikash BANTHIA ,  Hua AI

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/522

Abstract: Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.

公开(公告)号：US20170084486A1

公开(公告)日：2017-03-23

申请号：US15364780

申请日：2016-11-30

Applicant: Applied Materials, Inc.

Inventor： Bhushan N. ZOPE ,  Avgerinos V. GELATOS ,  Bo ZHENG ,  Yu LEI ,  Xinyu FU ,  Srinivas GANDIKOTA ,  Sang Ho YU ,  Mathew ABRAHAM

IPC: H01L21/768 ,  H01L21/285

Abstract: Methods for depositing a metal layer in a feature definition of a semiconductor device are provided. In one implementation, a method for depositing a metal layer for forming a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a metal layer on a substrate and annealing the metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the metal layer on the substrate, exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process until a predetermined thickness of the metal layer is achieved.

公开(公告)号：US20140120712A1

公开(公告)日：2014-05-01

申请号：US14147291

申请日：2014-01-03

Applicant: Applied Materials, Inc.

Inventor： Seshadri GANGULI ,  Srinivas GANDIKOTA ,  Yu LEI ,  Xinliang LU ,  Sang Ho YU ,  Hoon KIM ,  Paul F. MA ,  Mei CHANG ,  Maitreyee MAHAJANI ,  Patricia M. LIU

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  C23C16/06 ,  C23C16/32 ,  C23C16/42 ,  C23C16/45542 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966

Abstract: Embodiments provide methods for depositing metal-containing materials. The methods include deposition processes that form metal, metal carbide, metal silicide, metal nitride, and metal carbide derivatives by a vapor deposition process, including thermal decomposition, CVD, pulsed-CVD, or ALD. A method for processing a substrate is provided which includes depositing a dielectric material forming a feature definition in the dielectric material, depositing a work function material conformally on the sidewalls and bottom of the feature definition, and depositing a metal gate fill material on the work function material to fill the feature definition, wherein the work function material is deposited by reacting at least one metal-halide precursor having the formula MXY, wherein M is tantalum, hafnium, titanium, and lanthanum, X is a halide selected from the group of fluorine, chlorine, bromine, or iodine, and y is from 3 to 5.

Abstract translation: 实施例提供了沉积含金属材料的方法。 所述方法包括通过包括热分解，CVD，脉冲CVD或ALD的气相沉积工艺形成金属，金属碳化物，金属硅化物，金属氮化物和金属碳化物衍生物的沉积工艺。 提供了一种用于处理衬底的方法，其包括在电介质材料中形成形成特征定义的电介质材料，将功函数材料保形地沉积在特征定义的侧壁和底部上，以及在工作功能上沉积金属栅极填充材料 用于填充特征定义的材料，其中通过使至少一种具有式MXY的金属卤化物前体与其中M是钽，铪，钛和镧的金属卤化物前体反应沉积功函材料，X是选自氟 ，氯，溴或碘，y为3至5。