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公开(公告)号:US20150093891A1
公开(公告)日:2015-04-02
申请号:US14482601
申请日:2014-09-10
Applicant: Applied Materials, Inc.
Inventor: Bhushan N. ZOPE , Avgerinos V. GELATOS , Bo ZHENG , Yu LEI , Xinyu FU , Srinivas GANDIKOTA , Sang Ho YU , Mathew ABRAHAM
IPC: H01L21/768
CPC classification number: H01L21/76877 , C23C16/18 , H01L21/2855 , H01L21/28562 , H01L21/28568 , H01L21/76814 , H01L21/76843 , H01L21/76876 , H01L21/76879 , H01L21/76883
Abstract: Methods for depositing a metal layer in a feature definition of a semiconductor device are provided. In one implementation, a method for depositing a metal layer for forming a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a metal layer on a substrate and annealing the metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the metal layer on the substrate, exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process until a predetermined thickness of the metal layer is achieved.
Abstract translation: 提供了在半导体器件的特征定义中沉积金属层的方法。 在一个实施方案中,提供了一种用于沉积用于形成半导体器件的金属层的方法。 该方法包括进行循环金属沉积工艺以将金属层沉积在衬底上并使设置在衬底上的金属层退火。 循环金属沉积工艺包括将衬底暴露于沉积前体气体混合物以将金属层的一部分沉积在衬底上,将金属层的一部分暴露于等离子体处理工艺或氢退火工艺中,并重复暴露衬底 到沉积前体气体混合物并将金属层的该部分暴露于等离子体处理工艺或氢气退火工艺中,直到达到金属层的预定厚度。
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公开(公告)号:US20140011354A1
公开(公告)日:2014-01-09
申请号:US13956969
申请日:2013-08-01
Applicant: Applied Materials, Inc.
Inventor: Yu LEI , Xinyu FU , Anantha SUBRAMANI , Seshadri GANGULI , Srinivas GANDIKOTA
IPC: H01L21/02
CPC classification number: H01L21/02697 , B82Y40/00 , H01L21/28556 , H01L21/28562 , H01L21/7681 , H01L21/76834 , H01L21/76846 , H01L21/7685 , H01L21/76856 , H01L21/76858 , H01L21/76862 , H01L21/76864 , H01L21/76873 , H01L21/76877 , H01L21/76885 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
Abstract: Embodiments of the invention provide methods for forming materials on a substrate used for metal gate and other applications. In one embodiment, a method includes forming a cobalt stack over a barrier layer disposed on a substrate by depositing a cobalt layer during a deposition process, exposing the cobalt layer to a plasma to form a plasma-treated cobalt layer during a plasma process, and repeating the cobalt deposition process and the plasma process to form the cobalt stack containing a plurality of plasma-treated cobalt layers. The method further includes exposing the cobalt stack to an oxygen source gas to form a cobalt oxide layer from an upper portion of the cobalt stack during a surface oxidation process and heating the remaining portion of the cobalt stack to a temperature within a range from about 300° C. to about 500° C. to form a crystalline cobalt film during a thermal annealing crystallization process.
Abstract translation: 本发明的实施例提供了在用于金属栅极和其它应用的基板上形成材料的方法。 在一个实施例中,一种方法包括通过在沉积工艺期间沉积钴层而在设置在衬底上的势垒层上形成钴堆叠,在等离子体工艺期间将钴层暴露于等离子体以形成等离子体处理的钴层,以及 重复钴沉积工艺和等离子体工艺以形成含有多个等离子体处理的钴层的钴堆。 该方法还包括将钴堆叠暴露于氧源气体,以在表面氧化过程期间从钴堆叠的上部形成钴氧化物层,并将钴堆叠的剩余部分加热至约300 约500℃,以在热退火结晶过程中形成结晶钴膜。
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公开(公告)号:US20250079199A1
公开(公告)日:2025-03-06
申请号:US18458146
申请日:2023-08-29
Applicant: Applied Materials, Inc.
Inventor: Shiyu YUE , Sahil Jaykumar PATEL , Yu LEI , Wei LEI , Chih-Hsun HSU , Yi XU , Abulaiti HAIRISHA , Cong TRINH , Yixiong YANG , Ju Hyun OH , Aixi ZHANG , Xingyao GAO , Rongjun WANG
IPC: H01L21/67 , H01J37/32 , H01L21/3213
Abstract: A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.
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公开(公告)号:US20240420947A1
公开(公告)日:2024-12-19
申请号:US18210651
申请日:2023-06-16
Applicant: Applied Materials, Inc.
Inventor: Shiyu YUE , Jiajie CEN , Sahil Jaykumar PATEL , Zhimin QI , Ju Hyun OH , Aixi ZHANG , Xingyao GAO , Wei LEI , Yi XU , Yu LEI , Tsung-Han YANG , Xiaodong WANG , Xiangjin XIE , Yixiong YANG , Kevin KASHEFI , Rongjun WANG
IPC: H01L21/02 , H01L21/311
Abstract: A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl5, MoCl6) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.
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公开(公告)号:US20240178062A1
公开(公告)日:2024-05-30
申请号:US18083075
申请日:2022-12-16
Applicant: Applied Materials, Inc.
Inventor: Yi XU , Yu LEI , Aixi ZHANG , Rongjun WANG
IPC: H01L21/768 , H01L21/285
CPC classification number: H01L21/76877 , H01L21/28556
Abstract: A method of gap fill may include depositing a sacrificial Si layer in an opening of a feature and on a field of a substrate. In addition, the method may include depositing a metal layer in the opening and on the field, where at least a portion of the sacrificial Si layer is replaced with the metal layer. The method may also include depositing a metal gapfill material in the opening and on the field directly over the metal layer, where the metal gapfill material completely fills the opening.
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公开(公告)号:US20240088071A1
公开(公告)日:2024-03-14
申请号:US17944596
申请日:2022-09-14
Applicant: Applied Materials, Inc.
Inventor: Yi XU , Yu LEI , Zhimin QI , Aixi ZHANG , Xianyuan ZHAO , Wei LEI , Xingyao GAO , Shirish A. PETHE , Tao HUANG , Xiang CHANG , Patrick Po-Chun LI , Geraldine VASQUEZ , Dien-yeh WU , Rongjun WANG
IPC: H01L23/00
CPC classification number: H01L24/03 , H01L24/05 , H01L2224/03452 , H01L2224/03845 , H01L2224/05026 , H01L2224/05082 , H01L2224/05157 , H01L2224/05184 , H01L2924/01027 , H01L2924/01074 , H01L2924/04941 , H01L2924/0496 , H01L2924/059 , H01L2924/35121
Abstract: Methods for reducing resistivity of metal gapfill include depositing a conformal layer in an opening of a feature and on a field of a substrate with a first thickness of the conformal layer of approximately 10 microns or less, depositing a non-conformal metal layer directly on the conformal layer at a bottom of the opening and directly on the field using an anisotropic deposition process. A second thickness of the non-conformal metal layer on the field and on the bottom of the feature is approximately 30 microns or greater. And depositing a metal gapfill material in the opening of the feature and on the field where the metal gapfill material completely fills the opening without any voids.
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公开(公告)号:US20240014072A1
公开(公告)日:2024-01-11
申请号:US18212352
申请日:2023-06-21
Applicant: Applied Materials, Inc.
Inventor: Tsung-Han YANG , Zhimin QI , Yongqian GAO , Rongjun WANG , Yi XU , Yu LEI , Xingyao GAO , Chih-Hsun HSU , Xi CEN , Wei LEI , Shiyu YUE , Aixi ZHANG , Kai WU , Xianmin TANG
IPC: H01L21/768 , H01J37/32
CPC classification number: H01L21/76879 , H01J37/32449 , H01J37/32816 , H01J37/32422 , H01J2237/2001 , H01J37/321 , H01J2237/332
Abstract: A method of forming a semiconductor device structure includes forming a nucleation layer within at least one feature. The method includes exposing the nucleation layer to a nitrogen plasma treatment. The nitrogen plasma treatment preferentially treats the top field and sidewalls while leaving the bottom surface substantially untreated to encourage bottom up metal growth.
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公开(公告)号:US20230420295A1
公开(公告)日:2023-12-28
申请号:US18133102
申请日:2023-04-11
Applicant: Applied Materials, Inc.
Inventor: Tsung-Han YANG , Xingyao GAO , Shiyu YUE , Chih-Hsun HSU , Shirish PETHE , Rongjun WANG , Yi XU , Wei LEI , Yu LEI , Aixi ZHANG , Xianyuan ZHAO , Zhimin QI , Jiang LU , Xianmin TANG
IPC: H01L21/768 , H01L21/285 , H01J37/32
CPC classification number: H01L21/76877 , H01L21/76876 , H01L21/76865 , H01L21/2855 , H01J2237/338 , H01L21/76856 , H01L21/76861 , H01J37/32899 , H01L21/76843
Abstract: A method and apparatus for tungsten gap-fill in semiconductor devices are provided. The method includes performing a gradient oxidation process to oxidize exposed portions of a liner layer, wherein the gradient oxidation process preferentially oxidizes an overhang portion of the liner layer, which obstructs or blocks top openings of one or more features formed within a field region of a substrate. The method further includes performing an etchback process to remove or reduce the oxidized overhang portion of the liner layer, exposing the liner layer to a chemical vapor transport (CVT) process to remove metal oxide remaining from the gradient oxidation process and the etchback process, and performing a tungsten gap-fill process to fill or partially fill the one or more features.
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公开(公告)号:US20240087955A1
公开(公告)日:2024-03-14
申请号:US18241343
申请日:2023-09-01
Applicant: Applied Materials, Inc.
Inventor: Yi XU , Xianyuan ZHAO , Zhimin QI , Aixi ZHANG , Geraldine VASQUEZ , Dien-Yeh WU , Wei LEI , Xingyao GAO , Shirish PETHE , Wenting HOU , Chao DU , Tsung-Han YANG , Kyoung-Ho BU , Chen-Han LIN , Jallepally RAVI , Yu LEI , Rongjun WANG , Xianmin TANG
IPC: H01L21/768
CPC classification number: H01L21/76879 , H01L21/76843 , H01L21/76856 , H01L21/76876
Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.
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公开(公告)号:US20240018648A1
公开(公告)日:2024-01-18
申请号:US18220408
申请日:2023-07-11
Applicant: Applied Materials, Inc.
Inventor: Geraldine VASQUEZ , Yi XU , Dien-yeh WU , Aixi ZHANG , Jallepally RAVI , Yu LEI
IPC: C23C16/44 , H01J37/32 , C23C16/458
CPC classification number: C23C16/4408 , H01J37/32798 , C23C16/4586 , H01J2237/3321
Abstract: Embodiments of a purge ring for use in a process chamber are provided herein. In some embodiments, a purge ring includes: an annular body having an inner portion and an outer portion, wherein the inner portion includes an inner surface of the annular body, the inner surface comprising a first inner sidewall, a second inner sidewall, and a third inner sidewall, wherein the inner portion has an upper inner notch that defines the first inner sidewall and a lower inner notch that defines the second inner sidewall, wherein a third inner sidewall is disposed between the first inner sidewall and the second inner sidewall, and wherein the first inner sidewall and the second inner sidewall are disposed radially outward of the third inner sidewall.
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