公开(公告)号：US20110201149A1

公开(公告)日：2011-08-18

申请号：US13096719

申请日：2011-04-28

申请人： Nitin Kumar ,  Chi-I Lang ,  Tony Chiang ,  Zhi-wen Sun ,  Jinhong Tong

发明人： Nitin Kumar ,  Chi-I Lang ,  Tony Chiang ,  Zhi-wen Sun ,  Jinhong Tong

IPC分类号： H01L21/8239

CPC分类号： H01L45/145 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

摘要： Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

摘要翻译： 提供电阻式开关存储器元件，其可以包含由无电金属形成的化学金属电极和金属氧化物。 电阻式开关存储器元件可以表现出双稳态，并且可以用于高密度多层存储器集成电路中。 诸如镍基材料的无电导电材料可以选择性地沉积在硅晶片或其它合适的衬底上的导体上。 无电导电材料可以被氧化以形成用于电阻式开关存储元件的金属氧化物。 可以沉积多层导电材料，每层具有不同的氧化速率。 可以利用导电层的差异氧化速率来确保在制造期间形成所需厚度的金属氧化物层。

公开(公告)号：US07972897B2

公开(公告)日：2011-07-05

申请号：US11702966

申请日：2007-02-05

申请人： Nitin Kumar ,  Chi-I Lang ,  Tony Chiang ,  Zhi-wen Sun ,  Jinhong Tong

发明人： Nitin Kumar ,  Chi-I Lang ,  Tony Chiang ,  Zhi-wen Sun ,  Jinhong Tong

IPC分类号： H01L21/00

CPC分类号： H01L45/145 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

摘要： Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

摘要翻译： 提供电阻式开关存储器元件，其可以包含由无电金属形成的化学金属电极和金属氧化物。 电阻式开关存储器元件可以表现出双稳态，并且可以用于高密度多层存储器集成电路中。 诸如镍基材料的无电导电材料可以选择性地沉积在硅晶片或其它合适的衬底上的导体上。 无电导电材料可以被氧化以形成用于电阻式开关存储元件的金属氧化物。 可以沉积多层导电材料，每层具有不同的氧化速率。 可以利用导电层的差异氧化速率来确保在制造期间形成所需厚度的金属氧化物层。

公开(公告)号：US20100255678A1

公开(公告)日：2010-10-07

申请号：US12802701

申请日：2010-06-11

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of a copper seed layer on a wafer substrate without excessive build-up on the openings of each of the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. The method also comprises depositing a second portion of the metal seed layer while redistributing at least a portion of the bottom coverage material to the sidewalls of each recessed device feature, to provide a uniform seed layer coverage over the interior surface of the recessed device features.

摘要翻译： 我们公开了在包括多个凹入的装置特征的晶片衬底上沉积金属种子层的方法。 该方法包括在晶片衬底上沉积铜晶种层的第一部分，而不会在多个凹陷元件特征中的每一个的开口上过多地累积，同时获得底部覆盖而无需基本上溅射底面。 该方法还包括沉积金属种子层的第二部分，同时将底部覆盖材料的至少一部分重新分配到每个凹陷装置特征的侧壁，以在凹陷装置特征的内表面上提供均匀的种子层覆盖。

公开(公告)号：US07629198B2

公开(公告)日：2009-12-08

申请号：US11714334

申请日：2007-03-05

申请人： Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

发明人： Nitin Kumar ,  Jinhong Tong ,  Chi-I Lang ,  Tony Chiang ,  Prashant B. Phatak

IPC分类号： H01L21/00 ,  H01L21/16

CPC分类号： H01L45/04 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

摘要翻译： 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

公开(公告)号：US20090227067A1

公开(公告)日：2009-09-10

申请号：US12400655

申请日：2009-03-09

申请人： Pragati Kumar ,  Sean Barstow ,  Sunil Shanker ,  Tony Chiang

发明人： Pragati Kumar ,  Sean Barstow ,  Sunil Shanker ,  Tony Chiang

IPC分类号： H01L21/00

CPC分类号： H01L45/1633 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

摘要： Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements.

摘要翻译： 提供电阻式开关非易失性存储元件。 可以使用快速热退火技术来加热含金属层和用于存储元件的氧化物层。 在加热期间，氧化物层可能分解并与含金属层反应。 来自分解氧化物层的氧可以从含金属的层与金属形成金属氧化物。 所得到的金属氧化物可以表现出用于电阻式开关存储元件的电阻式开关。

公开(公告)号：US20080278990A1

公开(公告)日：2008-11-13

申请号：US12114667

申请日：2008-05-02

申请人： Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

发明人： Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

IPC分类号： G11C11/00 ,  H01L21/16

CPC分类号： H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165

摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or a Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

摘要翻译： 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。

公开(公告)号：US20070178682A1

公开(公告)日：2007-08-02

申请号：US11733671

申请日：2007-04-10

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/20

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括 步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被侵蚀或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。 在施加阻挡层时，使用标准溅射技术或使用离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）组合， 受离子影响的表面不会以对器件性能或寿命有害的量溅射。 随后，使用离子沉积溅射在增加的衬底偏置电压下施加阻挡材料的第二部分，这导致阻挡层材料的第一部分的再溅射（雕刻），同时能够进行更多的各向异性沉积新沉积的材料。 应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

公开(公告)号：US20070082508A1

公开(公告)日：2007-04-12

申请号：US11352077

申请日：2006-02-10

申请人： Tony Chiang ,  David Lazovsky ,  Thomas Boussie ,  Alexander Gorer

发明人： Tony Chiang ,  David Lazovsky ,  Thomas Boussie ,  Alexander Gorer

IPC分类号： H01L21/00 ,  H01L21/311 ,  H01L21/302

CPC分类号： H01L21/67011 ,  C23C14/54 ,  C23C16/4412 ,  C23C16/45544 ,  C23C16/4557 ,  C23C16/45578 ,  C23C16/4583 ,  C23C16/46 ,  C23C16/52 ,  H01J37/32449 ,  H01J37/32513 ,  H01J37/32724 ,  H01J2237/166 ,  H01J2237/20228 ,  H01J2237/20235 ,  H01L21/6715 ,  H01L21/76849 ,  H01L22/20 ,  H01L2924/0002 ,  Y10S438/907 ,  Y10S438/913 ,  Y10T137/8593 ,  H01L2924/00

摘要： The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

摘要翻译： 本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。 通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

公开(公告)号：US20060292846A1

公开(公告)日：2006-12-28

申请号：US11418800

申请日：2006-05-05

申请人： Gustavo Pinto ,  Tony Chiang

发明人： Gustavo Pinto ,  Tony Chiang

IPC分类号： H01L29/00 ,  H01L21/44 ,  C23C16/00

CPC分类号： H01L21/32051 ,  H01L21/67051 ,  H01L21/67294 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76871

摘要： Substrate processing systems and methods are described for processing substrates. The processing includes transferring electronic identification (ID) information of one or more materials contained in one or more processing subsystems. Materials are transferred between one or more material containers and respective one or more process cells during transfer events of the processing. Information or data of the transferred materials is automatically captured during the transfer events. Processing systems described include at least one identification (ID) device coupled to the subsystems. A data device is coupled to the ID device and to a device that performs the material transfers. The data device is configured to send or receive identification information of the subsystems from the ID device, and to send or receive information of transferred material from the material handling device.

摘要翻译： 描述了用于处理衬底的衬底处理系统和方法。 该处理包括传送包含在一个或多个处理子系统中的一个或多个材料的电子识别（ID）信息。 在处理的转移事件期间，材料在一个或多个材料容器和相应的一个或多个处理单元之间转移。 传输材料的信息或数据在传输事件期间自动捕获。 所描述的处理系统包括耦合到子系统的至少一个识别（ID）设备。 数据设备耦合到ID设备和执行物料传送的设备。 数据设备被配置为从ID设备发送或接收子系统的识别信息，并且从物料处理设备发送或接收传送的材料的信息。

公开(公告)号：US20060108320A1

公开(公告)日：2006-05-25

申请号：US11284572

申请日：2005-11-22

申请人： David Lazovsky ,  Tony Chiang ,  Majid Keshavarz

发明人： David Lazovsky ,  Tony Chiang ,  Majid Keshavarz

IPC分类号： H01L21/302 ,  C23F1/00

CPC分类号： H01L23/5329 ,  B82Y30/00 ,  H01L21/31 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76879 ,  H01L28/65 ,  H01L29/06 ,  H01L2924/0002 ,  Y10T428/249953 ,  H01L2924/00

摘要： Systems and methods for molecular self-assembly are provided. The molecular self-assembly receives a substrate that includes one or more regions of dielectric material. A molecularly self-assembled layer is formed on an exposed surface of the dielectric material. The molecularly self-assembled layer includes material(s) having a molecular characteristic and/or a molecular type that includes one or more of a molecular characteristic and/or a molecular type of a head group of molecules of the material, a molecular characteristic and/or a molecular type of a terminal group of molecules of the material, and a molecular characteristic and/or a molecular type of a linking group of molecules of the material. The molecular characteristic(s) and molecular type(s) are selected according to at least one pre-specified property of the molecularly self-assembled layer.

摘要翻译： 提供了分子自组装的系统和方法。 分子自组装接收包括电介质材料的一个或多个区域的衬底。 在介电材料的暴露表面上形成分子自组装层。 分子自组装层包括具有分子特征和/或分子类型的材料，其包括材料分子的头基团的分子特征和/或分子类型中的一种或多种，​​分子特征和 /或分子类型的材料的分子的末端基团，以及材料分子的连接基团的分子特征和/或分子类型。 分子特征和分子类型根据分子自组装层的至少一个预先确定的性质来选择。