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197 条记录 (耗时 0.036 秒)

    Method for depositing a diffusion barrier layer and a metal conductive layer
    1.
    发明授权
    Method for depositing a diffusion barrier layer and a metal conductive layer 有权
    沉积扩散阻挡层和金属导电层的方法

    公开(公告)号：US09390970B2

    公开(公告)日：2016-07-12

    申请号：US11733671

    申请日：2007-04-10

    申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

    发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

    IPC分类号： H01L21/768 ,  C23C14/04 ,  C23C14/16 ,  H01L21/285

    CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

    摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

    摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。第一保护层 的材料通过传统的溅射或离子沉积溅射沉积在衬底表面上，结合足够低的衬底偏压，其中施加了该层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

    Stress-engineered resistance-change memory device
    4.
    发明授权
    Stress-engineered resistance-change memory device 有权
    应力工程电阻变化记忆装置

    公开(公告)号：US08841745B2

    公开(公告)日：2014-09-23

    申请号：US13233937

    申请日：2011-09-15

    申请人： Michael Miller ,  Prashant Phatak ,  Tony Chiang

    发明人： Michael Miller ,  Prashant Phatak ,  Tony Chiang

    IPC分类号： H01L23/52 ,  H01L45/00 ,  H01L23/525 ,  H01L23/522 ,  H01L27/24

    CPC分类号： H01L45/1233 ,  H01L23/5228 ,  H01L23/525 ,  H01L27/2409 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A resistance-change memory device using stress engineering is described, including a first layer including a first conductive electrode, a second layer above the first layer including a resistive-switching element, a third layer above the second layer including a second conductive electrode, where a first stress is created in the switching element at a first interface between the first layer and the second layer upon heating the memory element, and where a second stress is created in the switching element at a second interface between the second layer and the third layer upon the heating. A stress gradient equal to a difference between the first stress and the second stress has an absolute value greater than 50 MPa, and a reset voltage of the memory element has a polarity relative to a common electrical potential that has a sign opposite the stress gradient when applied to the first conductive electrode.

    摘要翻译： 描述了使用应力工程的电阻变化存储器件，包括第一层，包括第一导电电极，第一层上方的第二层，包括电阻式开关元件，第二层上方的第三层包括第二导电电极， 在加热存储元件时在第一层和第二层之间的第一界面处在开关元件中产生第一应力，并且其中在第二层和第三层之间的第二界面处在开关元件中产生第二应力 加热。 等于第一应力和第二应力之间的差的应力梯度具有大于50MPa的绝对值，并且存储元件的复位电压具有相对于具有与应力梯度相反的符号的公共电位的极性， 施加到第一导电电极。

    ATOMIC LAYER DEPOSITION OF METAL OXIDE MATERIALS FOR MEMORY APPLICATIONS
    8.
    发明申请
    ATOMIC LAYER DEPOSITION OF METAL OXIDE MATERIALS FOR MEMORY APPLICATIONS 有权
    用于存储器应用的金属氧化物材料的原子层沉积

    公开(公告)号：US20130056702A1

    公开(公告)日：2013-03-07

    申请号：US13612000

    申请日：2012-09-12

    申请人： Yun Wang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik ,  Tony Chiang

    发明人： Yun Wang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik ,  Tony Chiang

    IPC分类号： H01L45/00 ,  B82Y10/00 ,  B82Y99/00

    CPC分类号： H01L45/145 ,  C23C16/40 ,  C23C16/45525 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

    摘要： Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.

    摘要翻译： 本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。 金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。 设置在金属氧化物层之间的界面有助于氧空位移动。 在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对准的晶界，其包含平行于电极界面延伸的许多晶界。 因此，氧空缺在切换期间被捕获和释放，而空位明显损失。 因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

    DEFECT GRADIENT TO BOOST NONVOLATILE MEMORY PERFORMANCE
    9.
    发明申请
    DEFECT GRADIENT TO BOOST NONVOLATILE MEMORY PERFORMANCE 有权
    缺陷增强非易失性存储器性能

    公开(公告)号：US20130056700A1

    公开(公告)日：2013-03-07

    申请号：US13223950

    申请日：2011-09-01

    申请人： Yun Wang ,  Tony Chiang ,  Imran Hashim

    发明人： Yun Wang ,  Tony Chiang ,  Imran Hashim

    IPC分类号： H01L45/00

    CPC分类号： H01L45/122 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1608

    摘要： Embodiments of the present invention generally relate to a resistive switching nonvolatile memory element that is formed in a resistive switching memory device that may be used in a memory array to store digital data. The memory element is generally constructed as a metal-insulator-metal stack. The resistive switching portion of the memory element includes a getter portion and/or a defect portion. In general, the getter portion is an area of the memory element that is used to help form, during the resistive switching memory device's fabrication process, a region of the resistive switching layer that has a greater number of vacancies or defects as compared to the remainder of resistive switching layer. The defect portion is an area of the memory element that has a greater number of vacancies or defects as compared to the remainder of the resistive switching layer, and is formed during the resistive switching memory device's fabrication process. The addition of the getter or defect portions in a formed memory device generally improves the reliability of the resistive switching memory device, improves the switching characteristics of the formed memory device and can eliminate or reduce the need for the time consuming additional post fabrication “burn-in” or pre-programming steps.

    摘要翻译： 本发明的实施例一般涉及一种电阻式开关非易失性存储元件，其形成在电阻式开关存储器件中，其可用于存储阵列中以存储数字数据。 存储元件通常构造为金属 - 绝缘体 - 金属叠层。 存储元件的电阻开关部分包括吸气部分和/或缺陷部分。 通常，吸气剂部分是存储元件的区域，其用于帮助在电阻式开关存储器件的制造过程期间形成与其余部分相比具有更多数量的空位或缺陷的电阻式开关层的区域 的电阻式开关层。 缺陷部分是与电阻开关层的其余部分相比具有更多数量的空位或缺陷的存储元件的区域，并且在电阻式开关存储器件的制造过程期间形成。 吸收剂或缺陷部分在形成的存储器件中的添加通常提高了电阻式开关存储器件的可靠性，改进了所形成的存储器件的开关特性，并且可以消除或减少对耗时的附加后制造烧坏的需要 或预编程步骤。