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    Embedded Nonvolatile Memory Elements Having Resistive Switching Characteristics
    1.
    发明申请
    Embedded Nonvolatile Memory Elements Having Resistive Switching Characteristics 有权
    具有电阻开关特性的嵌入式非易失性存储器元件

    公开(公告)号：US20140078808A1

    公开(公告)日：2014-03-20

    申请号：US13621371

    申请日：2012-09-17

    Applicant: Imran Hashim ,  Tony Chiang ,  Vidyut Gopal ,  Yun Wang

    Inventor： Imran Hashim ,  Tony Chiang ,  Vidyut Gopal ,  Yun Wang

    IPC: H01L27/24 ,  G11C11/21

    CPC classification number: H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

    Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

    Abstract translation: 提供了各自包括电阻式开关层和电流控制元件的非易失性存储器组件。 转向元件可以是与开关层串联连接的晶体管。 由转向元件提供的电阻控制允许使用需要低开关电压和电流的开关层。 包括这种开关层的存储器组件比例如需要高得多的开关电压的闪速存储器更容易嵌入到具有其它低电压组件（例如逻辑和数字信号处理组件）的集成电路芯片中。 在一些实施例中，所提供的非易失性存储器组件在小于约3.0V的开关电压和小于50微安的相应电流下工作。 存储元件可以包括设置在氮化钛电极和掺杂多晶硅电极之间的富含金属的氧化铪。 一个电极可以连接到晶体管的漏极或源极，而另一个电极连接到信号线。

    Planarization method using hybrid oxide and polysilicon CMP
    4.
    发明授权
    Planarization method using hybrid oxide and polysilicon CMP 有权
    使用混合氧化物和多晶硅CMP的平面化方法

    公开(公告)号：US07972962B2

    公开(公告)日：2011-07-05

    申请号：US12887182

    申请日：2010-09-21

    Applicant: David Matsumoto ,  Vidyut Gopal

    Inventor： David Matsumoto ,  Vidyut Gopal

    IPC: H01L21/461 ,  H01L21/302

    CPC classification number: H01L21/31053 ,  C09G1/02 ,  H01L21/76819

    Abstract: A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.

    Abstract translation: 提供了一种平面化半导体器件的方法。 半导体器件包括衬底，设置在衬底的表面上的第一和第二组件以及设置在第一和第二组件之间和之上的第一材料。 第一部件的高度大于第二部件的高度。 该方法包括在半导体器件上执行第一抛光步骤以去除第一部件的顶表面上方的第一材料，以去除第二部件的顶表面上方的第一材料，并且使第一部件的顶表面平整 。 该方法还包括在半导体器件上执行第二抛光步骤以平坦化第一和第二部件的顶表面。

    Dry etch release of MEMS structures
    5.
    发明授权
    Dry etch release of MEMS structures 失效
    MEMS结构的干蚀刻释放

    公开(公告)号：US06666979B2

    公开(公告)日：2003-12-23

    申请号：US10046593

    申请日：2001-10-29

    Applicant: Jeffrey D. Chinn ,  Vidyut Gopal ,  Sofiane Soukane ,  Toi Yue Becky Leung

    Inventor： Jeffrey D. Chinn ,  Vidyut Gopal ,  Sofiane Soukane ,  Toi Yue Becky Leung

    IPC: H01L2100

    CPC classification number: B81B3/0005 ,  B81B3/0008 ,  B81B2201/033 ,  B81C2201/016 ,  B81C2201/112

    Abstract: The present invention pertains to a method of fabricating a surface within a MEM which is free moving in response to stimulation. The free moving surface is fabricated in a series of steps which includes a release method, where release is accomplished by a plasmaless etching of a sacrificial layer material. An etch step is followed by a cleaning step in which by-products from the etch step are removed along with other contaminants which may lead to stiction. There are a series of etch and then clean steps so that a number of “cycles” of these steps are performed. Between each etch step and each clean step, the process chamber pressure is typically abruptly lowered, to create turbulence and aid in the removal of particulates which are evacuated from the structure surface and the process chamber by the pumping action during lowering of the chamber pressure. The final etch/clean cycle may be followed by a surface passivation step in which cleaned surfaces are passivated and/or coated.

    Abstract translation: 本发明涉及制造响应于刺激而自由移动的MEM内的表面的方法。 自由移动表面是在一系列步骤中制造的，其包括释放方法，其中通过牺牲层材料的无质子蚀刻来实现释放。 蚀刻步骤之后是清洁步骤，其中来自蚀刻步骤的副产物与可能导致静电的其它污染物一起被去除。 存在一系列蚀刻然后清洁步骤，使得执行这些步骤的许多“循环”。 在每个蚀刻步骤和每个清洁步骤之间，处理室压力通常突然降低，以产生湍流，并且有助于通过在降低腔室压力期间的泵送作用从结构表面和处理室排出的微粒去除。 最终的蚀刻/清洁循环之后可以是表面钝化步骤，其中清洁的表面被钝化和/或涂覆。

    Embedded nonvolatile memory elements having resistive switching characteristics
    6.
    发明授权
    Embedded nonvolatile memory elements having resistive switching characteristics 有权
    具有电阻开关特性的嵌入式非易失性存储元件

    公开(公告)号：US09129894B2

    公开(公告)日：2015-09-08

    申请号：US13621371

    申请日：2012-09-17

    Applicant: Imran Hashim ,  Tony Chiang ,  Vidyut Gopal ,  Yun Wang

    Inventor： Imran Hashim ,  Tony Chiang ,  Vidyut Gopal ,  Yun Wang

    IPC: G11C11/21 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00

    CPC classification number: H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

    Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

    Abstract translation: 提供了各自包括电阻式开关层和电流控制元件的非易失性存储器组件。 转向元件可以是与开关层串联连接的晶体管。 由转向元件提供的电阻控制允许使用需要低开关电压和电流的开关层。 包括这种开关层的存储器组件比例如需要高得多的开关电压的闪速存储器更容易嵌入到具有其它低电压组件（例如逻辑和数字信号处理组件）的集成电路芯片中。 在一些实施例中，所提供的非易失性存储器组件在小于约3.0V的开关电压和小于50微安的相应电流下工作。 存储元件可以包括设置在氮化钛电极和掺杂多晶硅电极之间的富含金属的氧化铪。 一个电极可以连接到晶体管的漏极或源极，而另一个电极连接到信号线。

    THIN FILM SOLAR CELL WITH CERAMIC HANDLING LAYER
    10.
    发明申请
    THIN FILM SOLAR CELL WITH CERAMIC HANDLING LAYER 有权
    薄膜太阳能电池与陶瓷处理层

    公开(公告)号：US20110186117A1

    公开(公告)日：2011-08-04

    申请号：US12766765

    申请日：2010-04-23

    Applicant: Ananda H. Kumar ,  Tirunelveli S. Ravi ,  Vidyut Gopal

    Inventor： Ananda H. Kumar ,  Tirunelveli S. Ravi ,  Vidyut Gopal

    IPC: H01L31/0236 ,  H01L31/18

    CPC classification number: H01L31/02167 ,  C03C3/091 ,  C03C3/097 ,  C03C8/08 ,  C03C8/14 ,  H01L31/02168 ,  H01L31/022425 ,  H01L31/02363 ,  H01L31/028 ,  H01L31/048 ,  H01L31/0682 ,  H01L31/072 ,  H01L31/0725 ,  H01L31/0747 ,  H01L31/1804 ,  H01L31/1896 ,  Y02E10/547 ,  Y02P70/521

    Abstract: A method for fabricating a photovoltaic (PV) cell panel wherein all PV cells are formed simultaneously on a two-dimensional array of monocrystalline silicon mother wafers affixed to a susceptor is disclosed. Porous silicon separation layers are anodized in the surfaces of the mother wafers. The porous film is then smoothed to form a suitable surface for epitaxial film growth. An epitaxial reactor is used to grow n- and p-type films forming the PV cell structures. A glass/ceramic handling layer is then formed on the PV cell structures. The PV cell structures with handling layers are then exfoliated from the mother wafer. The array of mother wafers may be reused multiple times, thereby reducing materials costs for the completed solar panels. The glass/ceramic handling layers provide structural integrity to the thin epitaxial solar cells during the separation process and subsequent handling.

    Abstract translation: 公开了一种用于制造光伏（PV）电池板的方法，其中所有PV电池同时形成在固定在基座上的单晶硅母晶片的二维阵列上。 在母晶片的表面上阳极氧化多孔硅分离层。 然后使多孔膜平滑以形成用于外延膜生长的合适表面。 使用外延反应器来生长形成PV电池结构的n型和p型膜。 然后在PV电池结构上形成玻璃/陶瓷处理层。 然后将具有处理层的PV电池结构从母晶片剥离。 母晶片的阵列可以重复使用多次，从而减少完成的太阳能电池板的材料成本。 玻璃/陶瓷处理层在分离过程和后续处理期间为薄的外延太阳能电池提供结构完整性。

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