公开(公告)号：US08158511B2

公开(公告)日：2012-04-17

申请号：US13068821

申请日：2011-05-20

Applicant: Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

Inventor： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC: H01L21/44

CPC classification number: H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

Abstract: A method of depositing a metal seed layer with underlying barrier layer on a wafer substrate comprising a plurality of recessed device features. A first portion of the barrier layer is deposited on the wafer substrate without excessive build-up of barrier layer material on the openings to the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. Subsequently, a metal seed layer is deposited using the same techniques used to deposit the barrier layer, to avoid excessive build up of metal seed layer material on the openings to the features, with minimal sputtering of the barrier layer surface.

Abstract translation: 一种在晶片衬底上沉积具有下层阻挡层的金属种子层的方法，包括多个凹陷的器件特征。 阻挡层的第一部分沉积在晶片衬底上，而不会在与多个凹陷器件特征的开口上过多地形成阻挡层材料，同时获得底部覆盖而无需基本上溅射底部表面。 随后，使用与沉积阻挡层相同的技术沉积金属种子层，以避免金属种子层材料在具有特征的开口上的过度积累，同时阻挡层表面的溅射最少。

公开(公告)号：US07989343B2

公开(公告)日：2011-08-02

申请号：US12802701

申请日：2010-06-11

Applicant: Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

Inventor： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC: H01L21/44

CPC classification number: H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

Abstract: We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of a copper seed layer on a wafer substrate without excessive build-up on the openings of each of the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. The method also comprises depositing a second portion of the metal seed layer while redistributing at least a portion of the bottom coverage material to the sidewalls of each recessed device feature, to provide a uniform seed layer coverage over the interior surface of the recessed device features.

Abstract translation: 我们公开了在包括多个凹入的装置特征的晶片衬底上沉积金属种子层的方法。 该方法包括在晶片衬底上沉积铜晶种层的第一部分，而不会在多个凹陷元件特征中的每一个的开口上过多地累积，同时获得底部覆盖而无需基本上溅射底面。 该方法还包括沉积金属种子层的第二部分，同时将底部覆盖材料的至少一部分重新分配到每个凹陷装置特征的侧壁，以在凹陷装置特征的内表面上提供均匀的种子层覆盖。

公开(公告)号：US20080166869A1

公开(公告)日：2008-07-10

申请号：US12075355

申请日：2008-03-10

Applicant: Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

Inventor： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC: H01L21/44

CPC classification number: H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

Abstract: A method of applying a sculptured copper seed layer on a semiconductor feature surface using ion deposition sputtering. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material.

Abstract translation: 使用离子沉积溅射在半导体特征表面上施加雕刻铜种子层的方法。 使用传统的溅射或离子沉积溅射将第一保护层材料沉积在衬底表面上，结合足够低的衬底偏压，使得施加层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。

公开(公告)号：US07074714B2

公开(公告)日：2006-07-11

申请号：US10981319

申请日：2004-11-03

Applicant: Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

Inventor： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC: H01L21/4763

CPC classification number: H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

Abstract translation: 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻的材料层的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。 使用传统的溅射或离子沉积溅射将第一保护层材料沉积在衬底表面上，结合足够低的衬底偏压，使得施加层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

公开(公告)号：US06919275B2

公开(公告)日：2005-07-19

申请号：US10796602

申请日：2004-03-08

Applicant: Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

Inventor： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen E. Chen ,  Barry L. Chin ,  Gene Y. Kohara ,  Zheng Xu ,  Hong Zhang

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/44 ,  H01L21/31

CPC classification number: H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

Abstract translation: 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻的材料层的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染。 使用传统的溅射或离子沉积溅射将第一保护层材料沉积在衬底表面上，结合足够低的衬底偏压，使得施加层的表面在保护层沉积期间不被腐蚀掉或被污染。 随后，使用离子沉积溅射在增加的衬底偏压下施加雕刻的第二材料层，以从材料的第一保护层的一部分和第二沉积材料层的一部分雕刻出形状。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层。

公开(公告)号：US5977607A

公开(公告)日：1999-11-02

申请号：US447362

申请日：1995-05-23

Applicant: Robert Louis Hodges ,  Frank Randolph Bryant ,  Fusen E. Chen ,  Che-Chia Wei

Inventor： Robert Louis Hodges ,  Frank Randolph Bryant ,  Fusen E. Chen ,  Che-Chia Wei

IPC: H01L21/32 ,  H01L21/762 ,  H01L29/00

CPC classification number: H01L21/32 ,  H01L21/76202

Abstract: A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.

Abstract translation: 提供一种用于形成集成电路的隔离氧化物区域的方法和根据该集成电路形成的集成电路。 在衬底的一部分上形成衬垫氧化物层。 在衬垫氧化物层上形成第一氮化硅层。 然后在第一氮化硅层上形成多晶硅缓冲层。 在多晶硅层上形成第二氮化硅层。 在第二氮化硅层上形成并图案化光致抗蚀剂层。 通过第二氮化硅层和多晶硅缓冲层蚀刻开口以暴露第一氮化硅层的一部分。 至少在开口中暴露的多晶硅缓冲层上形成第三氮化硅区域。 在开口中蚀刻第一氮化硅层。 然后在开口中形成场氧化物区域。

公开(公告)号：US5759869A

公开(公告)日：1998-06-02

申请号：US480936

申请日：1995-06-07

Applicant: Fusen E. Chen ,  Frank Randolph Bryant ,  Girish Anant Dixit

Inventor： Fusen E. Chen ,  Frank Randolph Bryant ,  Girish Anant Dixit

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/76804 ,  H01L21/31111 ,  H01L21/31116 ,  Y10S438/978

Abstract: A method for forming sloped contact corners of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A first oxide layer is formed over the integrated circuit. An insulating layer is formed over the oxide layer. The oxide and insulating layers are then patterned and etched to form a contact opening to expose a conductive region underlying a portion of the oxide layer. A second oxide layer is formed in the bottom of the contact opening. The insulating layer is then reflowed to form rounded contact corners after which the second oxide layer is removed.

Abstract translation: 公开了一种用于形成集成电路的倾斜接触角的方法，以及根据该集成电路形成的集成电路。 在集成电路上形成第一氧化物层。 在氧化物层上形成绝缘层。 然后对氧化物和绝缘层进行图案化和蚀刻以形成接触开口以暴露氧化物层的一部分下方的导电区域。 第二氧化物层形成在接触开口的底部。 然后将绝缘层回流以形成圆形接触角，之后除去第二氧化物层。

公开(公告)号：US5571752A

公开(公告)日：1996-11-05

申请号：US370456

申请日：1995-01-09

Applicant: Fusen E. Chen ,  Girish A. Dixit ,  Robert O. Miller

Inventor： Fusen E. Chen ,  Girish A. Dixit ,  Robert O. Miller

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/283

CPC classification number: H01L21/76843 ,  H01L21/76877 ,  Y10S257/915

Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. A first conductive structure is formed over the integrated circuit. A dielectric is formed over the first conductive structure having a contact opening exposing a portion of the underlying first conductive layer. A barrier layer is formed in the bottom of the contact opening. A second, substantially conformal conductive layer is formed by chemical vapor deposition over the dielectric layer; along the sidewalls and in the bottom of the contact opening. A third conductive layer is then formed over the second conductive layer wherein the third conductive layer does not fill the contact opening. The second and third conductive layers are etched to form an interconnect substantially over the contact opening.

Abstract translation: 提供了用于图案化集成电路的亚微米半导体层的方法，以及根据该集成电路形成的集成电路。 在集成电路上形成第一导电结构。 在第一导电结构上形成电介质，其具有暴露下面的第一导电层的一部分的接触开口。 阻挡层形成在接触开口的底部。 通过化学气相沉积在介电层上形成第二基本上保形的导电层; 沿着接触开口的侧壁和底部。 然后在第二导电层上形成第三导电层，其中第三导电层不填充接触开口。 第二和第三导电层被蚀刻以形成基本上在接触开口上的互连。

公开(公告)号：US5510294A

公开(公告)日：1996-04-23

申请号：US453563

申请日：1995-05-26

Applicant: Girish A. Dixit ,  Fusen E. Chen ,  Alexander Kalnitsky

Inventor： Girish A. Dixit ,  Fusen E. Chen ,  Alexander Kalnitsky

IPC: H01L21/768 ,  H01L21/44 ,  H01L21/467

CPC classification number: H01L21/76804 ,  Y10S148/105 ,  Y10S148/106 ,  Y10S438/978

Abstract: A method is provided for forming a via for multilevel metallization of an integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed over the integrated circuit. A first dielectric layer is then, formed over the first conductive layer. A second dielectric layer over the first dielectric layer and a second conductive layer is formed over the second dielectric layer. A photoresist layer is formed and patterned over the second conductive layer to expose a portion of the second conductive layer. The second conductive layer is etched to form an opening exposing a portion of the second dielectric layer. The second dielectric layer is then etched in the opening to form partially sloped sidewalls sloping outward at an upper surface of the dielectric layer. The photoresist layer is removed. The remaining second dielectric layer and the first electric layer is then anisotropically etched in the opening exposing the portion of the first conductive layer in the opening. The second conductive layer is then removed. A third conductive layer is deposited over the second dielectric layer and in the opening.

Abstract translation: 提供了一种用于形成用于集成电路的多层金属化的通孔的方法，以及根据该集成电路形成的集成电路。 在集成电路上形成第一导电层。 然后，在第一导电层上形成第一介电层。 第二电介质层上的第二电介质层和第二导电层形成在第二介电层上。 在第二导电层上形成并图案化光致抗蚀剂层以暴露第二导电层的一部分。 蚀刻第二导电层以形成露出第二介电层的一部分的开口。 然后在开口中蚀刻第二电介质层，以形成在电介质层的上表面向外倾斜的部分倾斜的侧壁。 去除光致抗蚀剂层。 然后将剩余的第二电介质层和第一电层在开口中各向异性地蚀刻，露出开口中的第一导电层的部分。 然后去除第二导电层。 第三导电层沉积在第二介电层上和开口中。

公开(公告)号：US5493144A

公开(公告)日：1996-02-20

申请号：US258609

申请日：1994-06-10

Applicant: Frank R. Bryant ,  Fusen E. Chen ,  Girish A. Dixit

Inventor： Frank R. Bryant ,  Fusen E. Chen ,  Girish A. Dixit

IPC: H01L21/82 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/525 ,  H01L27/04 ,  H01L23/48 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

Abstract: A method is provided for forming a field programmable device of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed. A first, fusible, dielectric layer is formed over the first conductive layer. The dielectric layer is patterned and etched to form a plurality of dielectric regions exposing portions of the first conductive layer. A second dielectric layer is then formed over the dielectric regions and the exposed portions of the first conductive layer. A plurality of contact openings through the second dielectric layer are formed to expose portions of the first conductive layer and portions of the dielectric regions. A second conductive layer is then formed over the second dielectric layer and in the contact openings.

Abstract translation: 提供一种用于形成半导体集成电路的现场可编程器件的方法和根据该集成电路形成的集成电路。 形成第一导电层。 在第一导电层上形成第一可熔介电层。 对介电层进行构图和蚀刻以形成露出第一导电层的部分的多个电介质区域。 然后在电介质区域和第一导电层的暴露部分上形成第二电介质层。 形成穿过第二电介质层的多个接触开口以暴露第一导电层和电介质区域的部分。 然后在第二介电层上和接触开口中形成第二导电层。