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    Material management in substrate processing
    1.
    发明申请
    Material management in substrate processing 审中-公开
    衬底加工中的材料管理

    公开(公告)号：US20060292846A1

    公开(公告)日：2006-12-28

    申请号：US11418800

    申请日：2006-05-05

    申请人： Gustavo Pinto ,  Tony Chiang

    发明人： Gustavo Pinto ,  Tony Chiang

    IPC分类号： H01L29/00 ,  H01L21/44 ,  C23C16/00

    CPC分类号： H01L21/32051 ,  H01L21/67051 ,  H01L21/67294 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76871

    摘要： Substrate processing systems and methods are described for processing substrates. The processing includes transferring electronic identification (ID) information of one or more materials contained in one or more processing subsystems. Materials are transferred between one or more material containers and respective one or more process cells during transfer events of the processing. Information or data of the transferred materials is automatically captured during the transfer events. Processing systems described include at least one identification (ID) device coupled to the subsystems. A data device is coupled to the ID device and to a device that performs the material transfers. The data device is configured to send or receive identification information of the subsystems from the ID device, and to send or receive information of transferred material from the material handling device.

    摘要翻译： 描述了用于处理衬底的衬底处理系统和方法。 该处理包括传送包含在一个或多个处理子系统中的一个或多个材料的电子识别（ID）信息。 在处理的转移事件期间，材料在一个或多个材料容器和相应的一个或多个处理单元之间转移。 传输材料的信息或数据在传输事件期间自动捕获。 所描述的处理系统包括耦合到子系统的至少一个识别（ID）设备。 数据设备耦合到ID设备和执行物料传送的设备。 数据设备被配置为从ID设备发送或接收子系统的识别信息，并且从物料处理设备发送或接收传送的材料的信息。

    METHOD AND APPARATUS FOR COMBINATORIALLY VARYING MATERIALS, UNIT PROCESS AND PROCESS SEQUENCE
    2.
    发明申请
    METHOD AND APPARATUS FOR COMBINATORIALLY VARYING MATERIALS, UNIT PROCESS AND PROCESS SEQUENCE 审中-公开
    用于组合变化材料的方法和装置，单元过程和过程序列

    公开(公告)号：US20070202614A1

    公开(公告)日：2007-08-30

    申请号：US11674132

    申请日：2007-02-12

    申请人： Tony Chiang ,  David Lazovsky ,  Kurt Weiner ,  Gustavo Pinto ,  Thomas Boussie ,  Alexander Gorer

    发明人： Tony Chiang ,  David Lazovsky ,  Kurt Weiner ,  Gustavo Pinto ,  Thomas Boussie ,  Alexander Gorer

    IPC分类号： H01L21/66

    CPC分类号： H01L22/20 ,  C23C14/54 ,  C23C16/52 ,  H01L21/76849 ,  H01L22/14 ,  Y02P80/40

    摘要： A method for analyzing and optimizing fabrication techniques using variations of materials, unit processes, and process sequences is provided. In the method, a subset of a semiconductor manufacturing process sequence and build is analyzed for optimization. During the execution of the subset of the manufacturing process sequence, the materials, unit processes, and process sequence for creating a certain structure is varied. During the combinatorial processing, the materials, unit processes, or process sequence is varied between the discrete regions of a semiconductor substrate, wherein within each of the regions the process yields a substantially uniform or consistent result that is representative of a result of a commercial manufacturing operation. A tool for optimizing a process sequence is also provided.

    摘要翻译： 提供了一种使用材料，单元过程和工艺顺序的变化来分析和优化制造技术的方法。 在该方法中，分析半导体制造过程序列和构建的子集以进行优化。 在执行制造过程序列的子集期间，用于创建特定结构的材料，单元过程和过程顺序是变化的。 在组合处理期间，材料，单元工艺或工艺顺序在半导体衬底的离散区域之间变化，其中在每个区域内，该工艺产生基本均匀或一致的结果，其代表商业制造的结果 操作。 还提供了用于优化处理顺序的工具。

    Combinatorial evaluation of dry semiconductor processes
    4.
    发明授权
    Combinatorial evaluation of dry semiconductor processes 有权
    干式半导体工艺组合评估

    公开(公告)号：US08647466B2

    公开(公告)日：2014-02-11

    申请号：US13095443

    申请日：2011-04-27

    申请人： Tony Chiang

    发明人： Tony Chiang

    IPC分类号： H01L21/306

    CPC分类号： H01L22/20

    摘要： Combinatorial evaluation of dry semiconductor processes is described, including rotating a mask comprising a plurality of apertures, wherein the mask is positioned between a dry semiconductor processing source and the substrate, and performing a dry semiconductor process through the apertures of the mask at a plurality of intervals during the rotating the mask to combinatorially create a plurality of processed regions on the substrate, wherein the apertures of the mask are arranged in such a way that the plurality of processed regions have different geometries relative to the processing source, and analyzing the processed regions to determine effects of time and geometry on the processed regions.

    摘要翻译： 描述了干式半导体工艺的组合评估，包括旋转包括多个孔的掩模，其中掩模位于干燥半导体处理源和衬底之间，并且通过多个掩模的掩模的孔径执行干燥半导体工艺 在旋转掩模期间的间隔以组合地在基底上产生多个经处理的区域，其中掩模的孔以这样的方式排列，使得多个经处理的区域相对于处理源具有不同的几何形状，并且分析处理区域 以确定时间和几何对处理区域的影响。

    Methods for forming nickel oxide films for use with resistive switching memory devices/US
    5.
    发明授权
    Methods for forming nickel oxide films for use with resistive switching memory devices/US 失效
    用于形成用于电阻式开关存储器件的氧化镍膜的方法/ US

    公开(公告)号：US08609475B2

    公开(公告)日：2013-12-17

    申请号：US13602637

    申请日：2012-09-04

    申请人： Zhi-Wen Sun ,  Tony Chiang ,  Chi-I Lang ,  Jinhong Tong

    发明人： Zhi-Wen Sun ,  Tony Chiang ,  Chi-I Lang ,  Jinhong Tong

    IPC分类号： H01L21/20 ,  H01L21/00 ,  H01L21/16 ,  H01L21/8229

    CPC分类号： H01L45/1253 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

    摘要： Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH)2 film on the substrate, where the forming the Ni(OH)2 occurs at the cathode; and annealing the Ni(OH)2 film to form the NiO film, where the NiO film forms a portion of a resistive switching memory element. In some embodiments, methods further include forming a top electrode on the NiO film and before the forming the Ni(OH)2 film, pre-treating the substrate. In some embodiments, methods are presented where the bottom electrode and the top electrode are a conductive material.

    摘要翻译： 在电阻式切换存储装置使用的基板上形成NiO膜的方法包括：制备镍离子溶液; 接收衬底，其中衬底包括底部电极，用作阴极的底部电极; 在衬底上形成Ni（OH）2膜，其中在阴极处形成Ni（OH）2; 并且还原Ni（OH）2膜以形成NiO膜，其中NiO膜形成电阻式开关存储元件的一部分。 在一些实施例中，方法还包括在NiO膜上形成顶部电极，并且在形成Ni（OH）2膜之前，预处理衬底。 在一些实施例中，呈现了底部电极和顶部电极为导电材料的方法。

    Resistive switching memory element including doped silicon electrode
    7.
    发明授权
    Resistive switching memory element including doped silicon electrode 有权
    电阻式开关存储元件包括掺杂硅电极

    公开(公告)号：US08502187B2

    公开(公告)日：2013-08-06

    申请号：US13454392

    申请日：2012-04-24

    申请人： Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

    发明人： Prashant Phatak ,  Tony Chiang ,  Michael Miller ,  Wen Wu

    IPC分类号： H01L47/00

    CPC分类号： H01L45/1616 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

    摘要： A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa.

    摘要翻译： 描述了包括掺杂硅电极的电阻式开关存储元件，其包括包括具有第一功函数的掺杂硅的第一电极，具有与第一功函数不同的第二功函数的第二电极在0.1和1.0电子伏特之间 eV），第一电极和第二电极之间的金属氧化物层，金属氧化物层使用体积介导的开关进行开关，并且具有大于4eV的带隙，并且存储元件从低电阻状态切换到高电阻 状态，反之亦然。

    NONVOLATILE RESISTIVE MEMORY ELEMENT WITH A NOVEL SWITCHING LAYER
    8.
    发明申请
    NONVOLATILE RESISTIVE MEMORY ELEMENT WITH A NOVEL SWITCHING LAYER 审中-公开
    具有新开关层的非易失性电阻记忆元件

    公开(公告)号：US20130134373A1

    公开(公告)日：2013-05-30

    申请号：US13305568

    申请日：2011-11-28

    申请人： Yun Wang ,  Imran Hashim ,  Tony Chiang

    发明人： Yun Wang ,  Imran Hashim ,  Tony Chiang

    IPC分类号： H01L45/00

    CPC分类号： G11C13/0007 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

    摘要： A nonvolatile resistive memory element has a novel variable resistance layer comprising one or more rare-earth oxides. The rare-earth oxide has a high k value, a high bandgap energy, and the ability to maintain an amorphous structure after thermal anneal processes. Thus, the novel variable resistance layer facilitates improved switching performance and reliability of the resistive memory element.

    摘要翻译： 非易失性电阻存储元件具有包含一种或多种稀土氧化物的新颖的可变电阻层。 稀土氧化物具有高k值，高带隙能，以及热退火工艺后保持非晶结构的能力。 因此，新颖的可变电阻层有助于提高电阻式存储元件的开关性能和可靠性。

    ATOMIC LAYER DEPOSITION OF HAFNIUM AND ZIRCONIUM OXIDES FOR MEMORY APPLICATIONS
    9.
    发明申请
    ATOMIC LAYER DEPOSITION OF HAFNIUM AND ZIRCONIUM OXIDES FOR MEMORY APPLICATIONS 有权
    用于存储器应用的铪和氧化锆的原子层沉积

    公开(公告)号：US20130071984A1

    公开(公告)日：2013-03-21

    申请号：US13236481

    申请日：2011-09-19

    申请人： Yun Wang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik ,  Tony Chiang

    发明人： Yun Wang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik ,  Tony Chiang

    IPC分类号： H01L45/00

    CPC分类号： H01L45/146 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1616

    摘要： Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal-rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material.

    摘要翻译： 本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。 用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其具有设置在金属氧化物本体层上或其上的金属氧化物缓冲层。 金属氧化物本体层含有富金属氧化物材料，金属氧化物缓冲层含有贫金属氧化物。 由于金属氧化物本体层比金属氧化物缓冲层氧化较少或更金属，所以金属氧化物本体层的电阻小于金属氧化物缓冲层的电阻。 在一个实例中，金属氧化物本体层含有富金属氧化铪材料，金属氧化物缓冲层含有贫金属氧化锆材料。