公开(公告)号：US20070054442A1

公开(公告)日：2007-03-08

申请号：US11223659

申请日：2005-09-08

Applicant: Po-Chih Liu ,  Chun-Hsiang Fang ,  Ming-Che Ho ,  Chia-Chien Lu

Inventor： Po-Chih Liu ,  Chun-Hsiang Fang ,  Ming-Che Ho ,  Chia-Chien Lu

IPC: H01L21/84 ,  H01L21/00

CPC classification number: H01L29/458 ,  H01L29/665 ,  H01L29/66757 ,  H01L29/78675

Abstract: A method for manufacturing a thin film transistor is provided. First, a poly-silicon island is formed on a substrate. Then, a patterned gate dielectric layer and a gate are formed on the poly-silicon island. Next, a source/drain is formed in the poly-silicon island beside the gate, wherein the region between the source/drain is a channel. Furthermore, a metal layer is formed on the substrate to cover the gate, the patterned gate dielectric layer and the poly-silicon island. Moreover, the metal layer above the source/drain will react with the poly-silicon island to form a silicide layer. Then, the non-reacted metal layer is removed. Afterwards, an inter-layer dielectric (ILD) is formed to cover the substrate. Then, the inter-layer dielectric above the source/drain is removed to form a source/drain contacting hole, wherein the silicide layer is used as an etching stopper.

Abstract translation: 提供了制造薄膜晶体管的方法。 首先，在基板上形成多晶硅岛。 然后，在多晶硅岛上形成图案化的栅介质层和栅极。 接下来，在栅极旁边的多晶硅岛中形成源极/漏极，其中源极/漏极之间的区域是沟道。 此外，在基板上形成金属层以覆盖栅极，图案化栅介质层和多晶硅岛。 此外，源极/漏极之上的金属层将与多晶硅岛反应形成硅化物层。 然后，除去未反应的金属层。 之后，形成层间电介质（ILD）以覆盖基板。 然后，除去源极/漏极之上的层间电介质以形成源极/漏极接触孔，其中硅化物层用作蚀刻停止层。

公开(公告)号：US20070051993A1

公开(公告)日：2007-03-08

申请号：US11222923

申请日：2005-09-08

Applicant: Ming-Che Ho ,  Yun-Pei Yang ,  Po-Chih Liu ,  Chia-Chien Lu

Inventor： Ming-Che Ho ,  Yun-Pei Yang ,  Po-Chih Liu ,  Chia-Chien Lu

IPC: H01L29/94 ,  G12B21/02

CPC classification number: H01L29/78609 ,  H01L29/4908 ,  H01L29/66757

Abstract: A method of forming a thin film transistor is provided. First, an amorphous silicon layer is formed on a substrate. Next, a first gate insulating layer is formed on the amorphous silicon layer. Then, an annealing process is performed so that the amorphous silicon layer is melted and re-crystallized to form a poly silicon layer. Next, the first insulating layer and the poly silicon layer are patterned to form an island. Then, a gate electrode is formed on the island. Finally, a source region and a drain region are formed inside the poly silicon layer of the island. After the annealing process is performed, the boundary between the poly silicon layer and the gate insulating layer becomes denser, so that the current leakage of the thin film transistor can be reduced.

Abstract translation: 提供一种形成薄膜晶体管的方法。 首先，在基板上形成非晶硅层。 接下来，在非晶硅层上形成第一栅极绝缘层。 然后，进行退火处理，使得非晶硅层熔融并再结晶以形成多晶硅层。 接下来，对第一绝缘层和多晶硅层进行图案化以形成岛。 然后，在岛上形成栅电极。 最后，在岛的多晶硅层的内部形成源极区域和漏极区域。 在进行退火处理之后，多晶硅层和栅极绝缘层之间的边界变得更致密，从而可以减小薄膜晶体管的漏电流。

公开(公告)号：US09099396B2

公开(公告)日：2015-08-04

申请号：US13291508

申请日：2011-11-08

Applicant: Yi-Wen Wu ,  Zheng-Yi Lim ,  Ming-Che Ho ,  Chung-Shi Liu

Inventor： Yi-Wen Wu ,  Zheng-Yi Lim ,  Ming-Che Ho ,  Chung-Shi Liu

IPC: H01L23/485 ,  H01L23/29 ,  H01L23/31 ,  H01L23/525 ,  H01L23/00

CPC classification number: H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/03424 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08503 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/2064 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Abstract translation: 半导体器件包括通过浸锡工艺在钝化后互连（PPI）结构的表面上形成的导电层。 聚合物层形成在导电层上并用开口图案化以暴露导电层的一部分。 然后在聚合物层的开口中形成焊料凸块以电连接到PPI结构。

公开(公告)号：US08993431B2

公开(公告)日：2015-03-31

申请号：US12778610

申请日：2010-05-12

Applicant: Chun-Lei Hsu ,  Ming-Che Ho ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Chun-Lei Hsu ,  Ming-Che Ho ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/44 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/1161 ,  H01L2224/11616 ,  H01L2224/11831 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/206 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method for fabricating bump structure forms an under-bump metallurgy (UBM) layer in an opening of an encapsulating layer, and then forms a bump layer on the UBM layer within the opening of the encapsulating layer. After removing excess material of the bump layer from the upper surface of the encapsulating layer, the encapsulating layer is removed till a top portion of the bump layer protrudes from the upper surface of the encapsulating layer.

Abstract translation: 一种用于制造凸块结构的方法在封装层的开口中形成凸起下金属（UBM）层，然后在封装层的开口内的UBM层上形成凸点层。 在从封装层的上表面除去突起层的多余材料之后，去除封装层直到凸起层的顶部从封装层的上表面突出。

公开(公告)号：US08865586B2

公开(公告)日：2014-10-21

申请号：US13344446

申请日：2012-01-05

Applicant: Yi-Wen Wu ,  Zheng-Yi Lim ,  Ming-Che Ho ,  Chung-Shi Liu

Inventor： Yi-Wen Wu ,  Zheng-Yi Lim ,  Ming-Che Ho ,  Chung-Shi Liu

IPC: H01L21/44 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L23/495 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L23/485 ,  H01L21/768 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/014

Abstract: A method includes forming a polymer layer over a metal pad, forming an opening in the polymer layer to expose a portion of the metal pad, and forming an under-bump-metallurgy (UBM). The UBM includes a portion extending into the opening to electrically couple to the metal pad.

Abstract translation: 一种方法包括在金属垫上形成聚合物层，在聚合物层中形成开口以暴露金属垫的一部分，并形成凸点下冶金（UBM）。 UBM包括延伸到开口中以电耦合到金属垫的部分。

公开(公告)号：US20130341786A1

公开(公告)日：2013-12-26

申请号：US13532402

申请日：2012-06-25

Applicant: Chun-Lei Hsu ,  Chung-Shi Liu ,  De-Yuan Lu ,  Ming-Che Ho ,  Yu-Feng Chen

Inventor： Chun-Lei Hsu ,  Chung-Shi Liu ,  De-Yuan Lu ,  Ming-Che Ho ,  Yu-Feng Chen

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15323 ,  H01L2924/15331 ,  H01L2924/15333 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/3651

Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. In one embodiment, a PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal pillars are coupled to the first packaged die. The metal pillars have a first portion proximate the first packaged die and a second portion disposed over the first portion. Each of the metal pillars is coupled to a solder joint proximate the second packaged die.

Abstract translation: 封装封装（PoP）器件和封装半导体管芯的方法被公开。 在一个实施例中，PoP器件包括第一封装管芯和耦合到第一封装管芯的第二封装管芯。 金属柱连接到第一封装的模具。 金属柱具有靠近第一封装管芯的第一部分和设置在第一部分上的第二部分。 每个金属支柱都联接到靠近第二包装模具的焊接接头。

公开(公告)号：US20130113094A1

公开(公告)日：2013-05-09

申请号：US13291508

申请日：2011-11-08

Applicant: Yi-Wen WU ,  Zheng-Yi LIM ,  Ming-Che HO ,  Chung-Shi LIU

Inventor： Yi-Wen WU ,  Zheng-Yi LIM ,  Ming-Che HO ,  Chung-Shi LIU

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/03424 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08503 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/2064 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Abstract translation: 半导体器件包括通过浸锡工艺在钝化后互连（PPI）结构的表面上形成的导电层。 聚合物层形成在导电层上并用开口图案化以暴露导电层的一部分。 然后在聚合物层的开口中形成焊料凸块以电连接到PPI结构。

公开(公告)号：US08405199B2

公开(公告)日：2013-03-26

申请号：US12832231

申请日：2010-07-08

Applicant: Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Ming-Che Ho ,  Chung-Shi Liu

Inventor： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Ming-Che Ho ,  Chung-Shi Liu

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11424 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13647 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2224/13655 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the disclosure includes a conductive pillar on a semiconductor die. A substrate is provided. A bond pad is over the substrate. A conductive pillar is over the bond pad. The conductive pillar has a top surface, edge sidewalls and a height. A cap layer is over the top surface of the conductive pillar. The cap layer extends along the edge sidewalls of the conductive pillar for a length. A solder material is over a top surface of the cap layer.

Abstract translation: 本公开的实施例包括半导体管芯上的导电柱。 提供基板。 焊盘在衬底上。 导电支柱位于接合垫上方。 导电柱具有顶表面，边缘侧壁和高度。 覆盖层在导电柱的顶表面之上。 盖层沿着导电柱的边缘侧壁延伸一段长度。 焊料材料在盖层的顶表面之上。

公开(公告)号：US20100193728A1

公开(公告)日：2010-08-05

申请号：US12186302

申请日：2008-08-05

Applicant: Song-Yuan CHANG ,  Ming-hui Lu ,  Ming-Che Ho

Inventor： Song-Yuan CHANG ,  Ming-hui Lu ,  Ming-Che Ho

IPC: C09K13/00

CPC classification number: C09K3/1463 ,  C09G1/02 ,  H01L21/3212

Abstract: An inhibitor composition according to the present invention at least comprises an imidazoline compound or a triazole compound or combinations thereof, and sarcosine and salt compounds thereof or combinations thereof. The inhibitor composition is applicable to chemical mechanical polishing so as to maintain a high removal rate of metal layers as well as suppress metal etching, thereby reducing polishing defects such as dishing, erosion and the like.

Abstract translation: 根据本发明的抑制剂组合物至少包含咪唑啉化合物或三唑化合物或其组合，以及其肌氨酸及其盐化合物或其组合。 抑制剂组合物适用于化学机械抛光，以保持金属层的高去除率以及抑制金属蚀刻，从而减少诸如凹陷，侵蚀等的抛光缺陷。

公开(公告)号：US08659155B2

公开(公告)日：2014-02-25

申请号：US12846353

申请日：2010-07-29

Applicant: Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chih-Wei Lin ,  Ching-Wen Chen ,  Yi-Wen Wu ,  Chia-Tung Chang ,  Ming-Che Ho ,  Chung-Shi Liu

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chih-Wei Lin ,  Ching-Wen Chen ,  Yi-Wen Wu ,  Chia-Tung Chang ,  Ming-Che Ho ,  Chung-Shi Liu

IPC: H01L23/48

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10145 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11827 ,  H01L2224/13006 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16507 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3651 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/05 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2224/05552

Abstract: The mechanism of forming a metal bump structure described above resolves the delamination issues between a conductive layer on a substrate and a metal bump connected to the conductive layer. The conductive layer can be a metal pad, a post passivation interconnect (PPI) layer, or a top metal layer. By performing an in-situ deposition of a protective conductive layer over the conductive layer (or base conductive layer), the under bump metallurgy (UBM) layer of the metal bump adheres better to the conductive layer and reduces the occurrence of interfacial delamination. In some embodiments, a copper diffusion barrier sub-layer in the UBM layer can be removed. In some other embodiments, the UBM layer is not needed if the metal bump is deposited by a non-plating process and the metal bump is not made of copper.

Abstract translation: 上述形成金属凸块结构的机构解决了基板上的导电层与连接到导电层的金属凸块之间的分层问题。 导电层可以是金属焊盘，后钝化互连（PPI）层或顶层金属层。 通过在导电层（或基底导电层）上进行保护性导电层的原位沉积，金属凸块的凸块下金属（UBM）层更好地粘附到导电层并减少界面分层的发生。 在一些实施例中，可以去除UBM层中的铜扩散阻挡子层。 在一些其它实施例中，如果通过非电镀工艺沉积金属凸块并且金属凸块不是由铜制成的，则不需要UBM层。