公开(公告)号：US09165905B2

公开(公告)日：2015-10-20

申请号：US13330422

申请日：2011-12-19

申请人： Hans Krueger ,  Alexander Schmajew ,  Alois Stelzl

发明人： Hans Krueger ,  Alexander Schmajew ,  Alois Stelzl

IPC分类号： H05K3/02 ,  H05K3/10 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  B81B7/00

CPC分类号： H01L24/94 ,  B81B7/007 ,  B81B2207/098 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/24991 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1068 ,  H01L2924/14 ,  H01L2924/1461 ,  Y10T29/49126 ,  H01L2224/81 ,  H01L2224/82

摘要： A plurality of unpackaged substrates connected to one another is disclosed. The stepped structures on and/or in a first main area of a first substrate include a plurality of integrated circuits. The stepped structures run between the integrated circuits. The first conductor tracks extend from at least some contact connections of the respective integrated circuits as far as the stepped structures. The first substrate is connected on the side of the first main area to a further substrate. The first substrate is severed from a second main area opposite to the first main area such that the first substrate is divided into a plurality of substrate pieces. Each substrate piece has one of the integrated circuits. The first conductor tracks are accessible in interspaces between the substrate pieces. The second conductor tracks are formed from the second main area. At least some of the second conductor tracks lead from the second main area over side walls of the substrate pieces as far as the first conductor tracks.

摘要翻译： 公开了彼此连接的多个未封装的基板。 第一基板的第一主区域和/或第一主区域中的阶梯结构包括多个集成电路。 阶梯式结构在集成电路之间运行。 第一导体轨道从各个集成电路的至少一些接触连接延伸到阶梯式结构。 第一基板在第一主区域的一侧连接到另一基板。 第一基板从与第一主区域相对的第二主区域切断，使得第一基板被分成多个基板块。 每个衬底片具有一个集成电路。 第一导体轨迹可在基片之间的间隙中接近。 第二导体轨道由第二主区域形成。 至少一些第二导体轨道从第二主区域超过衬底片的侧壁延伸，直到第一导体轨迹。

公开(公告)号：US20150187713A1

公开(公告)日：2015-07-02

申请号：US14658743

申请日：2015-03-16

申请人： Intel Corporation

发明人： Jiamiao Tang ,  Henry Xu ,  Shinichi Sakamoto

IPC分类号： H01L23/00 ,  H01L25/18 ,  H01L23/50

CPC分类号： H01L23/49811 ,  H01L21/50 ,  H01L21/56 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/24 ,  H01L24/25 ,  H01L24/43 ,  H01L24/82 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2021/60007 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/435 ,  H01L2224/43985 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/85138 ,  H01L2224/85815 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/48

摘要： Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.

摘要翻译： 本发明的一些实施例包括在支撑件和附接到支撑件的至少一个模具之间的连接结构。 模具包括在模具的表面上的多个管芯接合焊盘。 连接结构包括多个通孔和凹槽组合。 导电材料形成在通孔和沟槽组合中，以提供管芯接合焊盘和支撑件上的接合焊盘之间的连接。 描述和要求保护其他实施例。

公开(公告)号：US09003654B2

公开(公告)日：2015-04-14

申请号：US13039902

申请日：2011-03-03

申请人： Fabrice Jacquet ,  Sebastien Bolis ,  Damien Saint-Patrice

发明人： Fabrice Jacquet ,  Sebastien Bolis ,  Damien Saint-Patrice

IPC分类号： H01K3/10 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/0556 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/245 ,  H01L2224/32057 ,  H01L2224/82101 ,  H01L2224/82399 ,  H01L2224/82815 ,  H01L2224/82896 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2224/05552

摘要： A method for metalizing at least one blind via formed in at least one substrate, including: a) arranging at least one solid portion of electrically conductive material in the blind via, b) performing a thermal treatment of the solid portion of electrically conductive material, making it melt in the blind via, cooling the electrically conductive material, solidifying it in the blind via, and wherein, before carrying out step a), at least part of the walls of the blind via is covered with a material able to prevent wetting of said part of the walls of the blind via by the melted electrically conductive material obtained during the performance of step b), the solidified electrically conductive material obtained after carrying out step c) being able not to be secured to said non-wetting part of the walls of the blind via.

摘要翻译： 一种用于金属化在至少一个衬底中形成的至少一个盲孔的方法，包括：a）在所述盲孔中布置导电材料的至少一个实心部分，b）对导电材料的实心部分进行热处理， 使其在盲孔中熔化，冷却导电材料，将其固化在盲孔中，并且其中，在进行步骤a）之前，盲孔通孔的至少一部分壁被能够防止润湿的材料覆盖 通过在步骤b）执行期间获得的熔融导电材料的盲孔的所述部分壁的所述部分，在执行步骤c）之后获得的凝固的导电材料不能固定到所述非润湿部分 盲人通道的墙壁。

公开(公告)号：US20150076710A1

公开(公告)日：2015-03-19

申请号：US14551874

申请日：2014-11-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuei-Sung Chang ,  Chun-wen Cheng ,  Alexander Kalnitsky ,  Chia-Hua Chu

IPC分类号： H01L23/00 ,  H01L23/48

CPC分类号： H01L24/09 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/64 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/80 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/08145 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24145 ,  H01L2224/80896 ,  H01L2224/81 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1205 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/82 ,  H05K3/4661 ,  H01L2224/05552 ,  H01L2224/8203 ,  H01L2224/80001

摘要： The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.

摘要翻译： 本公开提供了堆叠半导体器件的一个实施例。 叠层半导体器件包括第一衬底; 第一衬底上的第一接合焊盘; 第二基板，包括在其上制造的第二电气装置; 在所述第二基板上方的所述第二电气装置上的第二接合焊盘，所述第二接合焊盘电连接到所述第二电气装置; 所述第二接合焊盘上的第二绝缘层具有顶表面，所述第二绝缘层朝向所述第一基板的所述第一接合焊盘接合; 以及从第一接合焊盘相反的表面穿过第一基板延伸并穿过第二绝缘层的顶表面延伸到第二接合焊盘的贯通基板通孔（“TSV”）。

公开(公告)号：US20150031172A1

公开(公告)日：2015-01-29

申请号：US14279891

申请日：2014-05-16

申请人： Hamilton Sundstrand Corporation

发明人： Rainer J. Seidel ,  Thomas E. Gerhaeusser

IPC分类号： H01L21/768 ,  H01L23/00

CPC分类号： H01L21/76838 ,  H01L21/76801 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/0603 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/24998 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/82101 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2924/01029 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30101 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method is described for interconnecting first, 27, and second, 22, components on a substrate, 21. The method comprises attaching said first component, 27, to said substrate, attaching said second component, 22, to said substrate, 21, said first and second components being positioned relative to each other on said substrate to form a gap, 31, therebetween. The method further comprises the step of depositing a layer, 24, of electrically insulating material in said gap, and electrically connecting said first component, 27, with said second component, 22, by depositing, upon said electrically insulating layer, a layer of electrically conducting material, 26, which is in contact with and extends from a surface of said first electronic component, across said gap, 31, and said layer of electrically insulating material, 24, and to a surface of said second electronic component, 22. The method is characterized in that a plasma deposition process is used to deposit at least one of said layers of material.

摘要翻译： 描述了用于将第一部件27和第二部件22与第二部件22连接在一起的方法。该方法包括将所述第一部件27附着到所述基板，将所述第二部件22附接到所述基板21，所述第二部件 第一和第二部件相对于彼此定位在所述基板上，以在它们之间形成间隙31。 该方法还包括以下步骤：在所述间隙中沉积电绝缘材料层24，并且通过在所述电绝缘层上沉积一层电学上电而将所述第一组分27与所述第二组分22电连接 导电材料26，其与所述第一电子部件的表面接触并从所述第一电子部件的表面延伸穿过所述间隙31，以及所述电绝缘材料层24以及所述第二电子部件22的表面。 方法的特征在于使用等离子体沉积工艺沉积所述材料层中的至少一个。

公开(公告)号：US08900894B2

公开(公告)日：2014-12-02

申请号：US13596842

申请日：2012-08-28

申请人： Ewald Karl Michael Guenther ,  Jörg Erich Sorg ,  Norbert Stath

发明人： Ewald Karl Michael Guenther ,  Jörg Erich Sorg ,  Norbert Stath

IPC分类号： H01L21/00 ,  H01L33/62 ,  H01L33/52 ,  H01L23/00 ,  H01L33/54 ,  H01L33/50

CPC分类号： H01L33/62 ,  H01L24/24 ,  H01L24/82 ,  H01L33/508 ,  H01L33/52 ,  H01L33/54 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/82007 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2924/00

摘要： In a method for producing a radiation-emitting optoelectronic component, a semiconductor chip is mounted by a first main area onto a carrier body and is electrically conductively connected at a first contact area to a first connection region, and a transparent electrically insulating encapsulation layer is applied to the chip and the carrier body. A first cutout in the encapsulation layer for at least partly uncovering a second contact area of the chip is produced, and a second cutout in the encapsulation layer for at least partly uncovering a second connection region of the carrier body is produced. Finally, an electrically conductive layer, which electrically conductively connects the second contact area of the semiconductor chip and the second connection region of the carrier body, is applied.

摘要翻译： 在制造发射光电子部件的方法中，半导体芯片由第一主区域安装到载体主体上，并且在第一接触区域与第一连接区域导电连接，并且透明电绝缘封装层是 应用于芯片和载体主体。 产生用于至少部分地露出芯片的第二接触区域的封装层中的第一切口，并且产生用于至少部分地露出载体主体的第二连接区域的封装层中的第二切口。 最后，施加导电连接半导体芯片的第二接触区域和载体主体的第二连接区域的导电层。

公开(公告)号：US08890333B2

公开(公告)日：2014-11-18

申请号：US13886758

申请日：2013-05-03

申请人： Samsung Electronics Co., Ltd.

发明人： SeokHyun Lee ,  Jin-Woo Park ,  Taesung Park

IPC分类号： H01L29/40

CPC分类号： H01L21/76892 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76822 ,  H01L21/76894 ,  H01L21/82 ,  H01L23/3185 ,  H01L23/48 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/821 ,  H01L2224/82365 ,  H01L2224/95 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/01029 ,  H05K3/4661 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/00

摘要： Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip.

摘要翻译： 堆叠的半导体芯片包括将半导体芯片电连接到每个芯片的无接线的互连。 在半导体芯片之间的粘合层中的开口可以提供用于从沿着半导体芯片的侧壁绝缘层的一个半导体芯片上的接合焊盘沿另一个半导体芯片的侧壁绝缘层到接合焊盘的互连的路径 另一个半导体芯片。

公开(公告)号：US20140264786A1

公开(公告)日：2014-09-18

申请号：US14292925

申请日：2014-06-01

申请人： STATS ChipPAC, Ltd.

发明人： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

IPC分类号： H01L23/522 ,  H01L23/00

CPC分类号： H01L23/522 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/30 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13157 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL.

摘要翻译： 半导体器件具有具有倾斜侧表面的第一半导体管芯。 第一半导体管芯安装到临时载体上。 RDL从第一半导体管芯的后表面沿着第一半导体管芯的倾斜侧表面延伸到载体。 密封剂沉积在载体上，RDL的一部分沿着倾斜的侧表面沉积。 第一半导体管芯的背面和RDL的一部分没有密封剂。 移除临时载体。 在第一半导体管芯的密封剂和暴露的有源表面上形成互连结构。 RDL电连接到互连结构。 第二半导体管芯安装在第一半导体管芯的后表面上。 第二半导体管芯具有与RDL电连接的突起。

公开(公告)号：US08803325B2

公开(公告)日：2014-08-12

申请号：US13613983

申请日：2012-09-13

申请人： Seong Cheol Kim

发明人： Seong Cheol Kim

IPC分类号： H01L23/538

CPC分类号： H01L23/5384 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/525 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25105 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05552

摘要： A stacked semiconductor package includes a plurality of semiconductor chips each including a substrate having one surface, the other surface which faces away from the one surface and side surfaces which connect the one surface and the other surface, through-silicon vias which pass through the one surface and the other surface of the substrate, repair pads which are exposed on the side surfaces of the substrate, and wiring lines which electrically connect the through-silicon vias with the repair pads, the plurality of semiconductor chips being stacked such that through-silicon vias of the semiconductor chips are connected with one another; and interconnections electrically connecting the repair pads of the semiconductor chips.

摘要翻译： 堆叠的半导体封装包括多个半导体芯片，每个半导体芯片包括具有一个表面的基板，另一个表面背离该一个表面以及连接一个表面和另一个表面的侧表面，穿过一个表面的通孔硅通孔 衬底的表面和另一个表面，暴露在衬底的侧表面上的修补焊盘以及将穿硅通孔与修补焊盘电连接的布线，多个半导体芯片被堆叠成使得通过硅 半导体芯片的通孔彼此连接; 以及电连接半导体芯片的修补焊盘的互连。

公开(公告)号：US08796137B2

公开(公告)日：2014-08-05

申请号：US12822488

申请日：2010-06-24

申请人： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

发明人： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

IPC分类号： H01L21/44

CPC分类号： H01L23/522 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/30 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13157 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL.

摘要翻译： 半导体器件具有具有倾斜侧表面的第一半导体管芯。 第一半导体管芯安装到临时载体上。 RDL从第一半导体管芯的后表面沿着第一半导体管芯的倾斜侧表面延伸到载体。 密封剂沉积在载体上，RDL的一部分沿着倾斜的侧表面沉积。 第一半导体管芯的背面和RDL的一部分没有密封剂。 移除临时载体。 在第一半导体管芯的密封剂和暴露的有源表面上形成互连结构。 RDL电连接到互连结构。 第二半导体管芯安装在第一半导体管芯的后表面上。 第二半导体管芯具有与RDL电连接的突起。