公开(公告)号：US09577948B2

公开(公告)日：2017-02-21

申请号：US14122078

申请日：2012-06-01

Applicant: Byoung Hoon Kim ,  Seong Cheol Kim

Inventor： Byoung Hoon Kim ,  Seong Cheol Kim

IPC: G06F15/173 ,  H04L12/911 ,  H04L12/24 ,  H04L29/14 ,  H04L29/12

CPC classification number: H04L47/70 ,  H04L41/082 ,  H04L61/1511 ,  H04L69/40

Abstract: An apparatus for connecting to an update server includes an update unit configured to connect to the update server over a network using a pre-stored domain name address of the update server and an IP address acquisition unit configured to acquire an IP address of the connected update server. The IP address acquired by the IP address acquisition unit is stored as a trusted IP address in a storage unit. The apparatus further includes a reconnection processing unit configured to fetch the trusted IP address of the update server and try connecting to the update server using the trusted IP address in the case of failure to connect to the update server using the pre-stored domain name address.

Abstract translation: 用于连接到更新服务器的装置包括：更新单元，被配置为使用预先存储的更新服务器的域名地址通过网络连接到更新服务器;以及IP地址获取单元，被配置为获取所连接的更新的IP地址 服务器。 由IP地址获取单元获取的IP地址作为可信IP地址存储在存储单元中。 该装置还包括：重新连接处理单元，被配置为获取更新服务器的可信IP地址，并且在使用预存的域名地址未能连接到更新服务器的情况下尝试使用可信IP地址连接到更新服务器 。

公开(公告)号：US20100289136A1

公开(公告)日：2010-11-18

申请号：US12640125

申请日：2009-12-17

Applicant: Seong Cheol Kim

Inventor： Seong Cheol Kim

IPC: H01L23/34 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/13009 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: A semiconductor package comprises a semiconductor chip, through electrodes and cooling parts. The semiconductor chip has bonding pads on an upper surface thereof. The through-electrodes are formed in the semiconductor chip. The cooling parts are formed in the semiconductor chip and on the upper surface of the semiconductor chip in order to dissipate heat.

Abstract translation: 半导体封装包括通过电极和冷却部件的半导体芯片。 半导体芯片在其上表面具有接合焊盘。 贯通电极形成在半导体芯片中。 冷却部件形成在半导体芯片中并在半导体芯片的上表面上以散热。

公开(公告)号：US20090189267A1

公开(公告)日：2009-07-30

申请号：US12059308

申请日：2008-03-31

Applicant: Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Ha Na Lee

Inventor： Sung Min Kim ,  Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Ha Na Lee

IPC: H01L23/02 ,  H01L23/52

CPC classification number: H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05552 ,  H01L2224/06051 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/13099

Abstract: A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips.

Abstract translation: 具有适合堆叠半导体芯片的芯片选择结构的半导体芯片包括半导体芯片体和芯片选择结构。 芯片选择结构包括设置在半导体芯片主体上的芯片选择焊盘，电连接到芯片选择焊盘的主通孔以及置于主通孔和芯片选择焊盘之间的副通孔。 可以通过抵消堆叠的半导体芯片来堆叠各自具有相同芯片选择结构的多个半导体芯片。

公开(公告)号：US07355286B2

公开(公告)日：2008-04-08

申请号：US11485226

申请日：2006-07-12

Applicant: Seong Cheol Kim

Inventor： Seong Cheol Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/563 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/10125 ,  H01L2224/13027 ,  H01L2224/141 ,  H01L2224/16237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A flip chip bonded package applicable to a fine pitch technology uses, inter alia, insulative posts instead of using conductive bumps, which correspond to electrodes one by one. The insulative posts are assigned to every two bonding pads for the sake of flip chip bonding. This makes it possible to fabricate flip chip bonded packages very easily without modifying conventional processes. Larger bumps are provided even in the case of a technology having the same pad size and pitch during flip chip bonding. This makes the subsequent attachment process easy and reduces the defective ratio. The insulative posts, when made of a polymer, also act as stress buffers. This improves the reliability of the package.

Abstract translation: 适用于细间距技术的倒装芯片接合封装尤其使用绝缘柱而不是使用与电极对应的导电凸块。 为了倒装芯片接合，绝缘柱分配给每两个焊盘。 这使得可以非常容易地制造倒装芯片粘合包装而不改变常规工艺。 即使在倒装芯片接合期间具有相同焊盘尺寸和间距的技术的情况下也提供更大的凸块。 这使得随后的附接过程变得容易并且减少了缺陷率。 当由聚合物制成时，绝缘柱也作为缓冲层。 这提高了包装的可靠性。

公开(公告)号：US20070228564A1

公开(公告)日：2007-10-04

申请号：US11485226

申请日：2006-07-12

Applicant: Seong Cheol Kim

Inventor： Seong Cheol Kim

IPC: H01L23/48

CPC classification number: H01L21/563 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/10125 ,  H01L2224/13027 ,  H01L2224/141 ,  H01L2224/16237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A flip chip bonded package applicable to a fine pitch technology uses, inter alia, insulative posts instead of using conductive bumps, which correspond to electrodes one by one. The insulative posts are assigned to every two bonding pads for the sake of flip chip bonding. This makes it possible to fabricate flip chip bonded packages very easily without modifying conventional processes. Larger bumps are provided even in the case of a technology having the same pad size and pitch during flip chip bonding. This makes the subsequent attachment process easy and reduces the defective ratio. The insulative posts, when made of a polymer, also act as stress buffers. This improves the reliability of the package.

Abstract translation: 适用于细间距技术的倒装芯片接合封装尤其使用绝缘柱而不是使用与电极对应的导电凸块。 为了倒装芯片接合，绝缘柱分配给每两个焊盘。 这使得可以非常容易地制造倒装芯片粘合包装而不改变常规工艺。 即使在倒装芯片接合期间具有相同焊盘尺寸和间距的技术的情况下也提供更大的凸块。 这使得随后的附接过程变得容易并且减少了缺陷率。 当由聚合物制成时，绝缘柱也作为缓冲层。 这提高了包装的可靠性。

公开(公告)号：US08823161B2

公开(公告)日：2014-09-02

申请号：US13243575

申请日：2011-09-23

Applicant: Seong Cheol Kim

Inventor： Seong Cheol Kim

IPC: H01L23/04 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface, a chip pad disposed on the first surface of the substrate, and a through-silicon via (TSV) including a plurality of sub vias electrically connected to the chip pad at different positions.

Abstract translation: 半导体芯片包括具有第一表面和与第一表面相对的第二表面的基板，设置在基板的第一表面上的芯片焊盘以及包括多个子通孔的贯穿硅通孔（TSV），该多个子通孔电连接到 芯片垫在不同的位置。

公开(公告)号：US08338921B2

公开(公告)日：2012-12-25

申请号：US13289365

申请日：2011-11-04

Applicant: Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Sung Min Kim ,  Hyeong Seok Choi ,  Ha Na Lee ,  Tac Keun Oh ,  Sang Joon Lim

Inventor： Chang Jun Park ,  Kwon Whan Han ,  Seong Cheol Kim ,  Sung Min Kim ,  Hyeong Seok Choi ,  Ha Na Lee ,  Tac Keun Oh ,  Sang Joon Lim

IPC: H01L23/48 ,  H01L21/28

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

Abstract: A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

Abstract translation: 提出了具有增强的EMF屏蔽的热交换效率的晶片级芯片级封装。 晶片级芯片级封装包括半导体芯片，绝缘层和金属板。 半导体芯片在其上表面上具有多个接合焊盘。 绝缘层设置在半导体芯片的上表面上，并且具有暴露接合焊盘的一些部分的开口。 金属板覆盖绝缘层的上表面和半导体芯片的侧面，其中金属板与接合焊盘电绝缘。

公开(公告)号：US08237291B2

公开(公告)日：2012-08-07

申请号：US12647625

申请日：2009-12-28

Applicant: Seong Cheol Kim

Inventor： Seong Cheol Kim

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A stack package includes a substrate having an upper surface and a lower surface which faces away from the upper surface, a lower stack group, an upper stack group, and connection members. The lower stack group is attached to the upper surface of the substrate and includes at least two semiconductor chips which are stacked in a face-up type to form on or more steps. The upper stack group is disposed over the lower stack group and includes at least two semiconductor chips which are stacked in a face-down type in such a way as to form one or more steps whose direction mirrors the direction of the at least one step of the lower stack group. The connection members electrically connect the semiconductor chips of the lower and upper stack groups to the substrate.

Abstract translation: 堆叠包括具有上表面和背表面的下表面的基板，下堆叠组，上堆叠组和连接构件。 下堆叠组附接到基板的上表面，并且包括至少两个半导体芯片，其以面朝上的类型堆叠以形成一个或多个台阶。 上堆叠组布置在下堆叠组上方，并且包括至少两个半导体芯片，其以面朝下的方式堆叠，以形成一个或多个步骤，其方向反映至少一个步骤的方向 下堆叠组。 连接构件将下堆叠组和上堆叠组的半导体芯片电连接到衬底。

公开(公告)号：US08198719B2

公开(公告)日：2012-06-12

申请号：US12835927

申请日：2010-07-14

Applicant: Seong Cheol Kim

Inventor： Seong Cheol Kim

IPC: H01L23/04 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/10126 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A semiconductor chip includes a semiconductor chip body, a through-silicon via and a silicon pattern. The semiconductor chip body has a first surface and a second surface facing away from the first surface. The through-silicon via is formed to pass through the semiconductor chip body and has a metal layer and an insulation layer which protrude from the second surface. The silicon pattern is formed on a sidewall of the protruding through-silicon via.

Abstract translation: 半导体芯片包括半导体芯片体，穿硅通孔和硅图案。 半导体芯片本体具有第一表面和第二表面，该第二表面背离第一表面。 穿通硅通孔被形成为穿过半导体芯片体并且具有从第二表面突出的金属层和绝缘层。 硅图案形成在突出的硅通孔的侧壁上。

公开(公告)号：US08183689B2

公开(公告)日：2012-05-22

申请号：US11760010

申请日：2007-06-08

Applicant: Seong Cheol Kim ,  Myung Geun Park

Inventor： Seong Cheol Kim ,  Myung Geun Park

IPC: H01L23/48

CPC classification number: H05K1/111 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15311 ,  H05K2201/09381 ,  H05K2201/099 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/13099 ,  H01L2224/0401

Abstract: A printed circuit board and a flip chip package using the same are designed to minimize thermal stress due to different thermal coefficients present in areas having metal lines and solder resist versus other areas on the printed circuit board. The printed circuit board includes an insulation layer; a first metal line formed on one surface of the insulation layer and having at one end thereof a bump land and a projection which integrally extends from the bump land; a second metal line formed on the other surface of the insulation layer and having at one end thereof a ball land; a via metal line formed through the insulation layer to connect the first and second metal lines to each other; and solder resists formed on the upper and lower surfaces of the insulation layer to expose the bump land and the ball land.

Abstract translation: 印刷电路板和使用其的倒装芯片封装被设计成使得存在于具有金属线和阻焊剂的区域中存在的不同热系数与印刷电路板上的其它区域的热应力最小化。 印刷电路板包括绝缘层; 形成在所述绝缘层的一个表面上的第一金属线，并且在其一个端部处具有凸起区域和从所述凸起区域整体延伸的突起; 形成在所述绝缘层的另一个表面上并且在其一个端部处具有球形区域的第二金属线; 通过所述绝缘层形成的通孔金属线，以将所述第一和第二金属线彼此连接; 以及形成在绝缘层的上表面和下表面上的阻焊剂，以暴露凸起部分和球状区域。