知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

37 records (took 0.056 seconds)

    Methods of fabricating semiconductor package
    1.
    发明授权
    Methods of fabricating semiconductor package 有权

    公开(公告)号：US12046526B2

    公开(公告)日：2024-07-23

    申请号：US17735471

    申请日：2022-05-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Ho Park ,  Jin-Woo Park ,  Jae Gwon Jang ,  Gwang Jae Jeon

    IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

    CPC classification number: H01L23/3128 ,  H01L21/565 ,  H01L24/19 ,  H01L23/293

    Abstract: Methods of fabricating a semiconductor package may include forming a first barrier layer on a first carrier, forming a sacrificial layer, including an opening that exposes at least a portion of the first barrier layer, on the first barrier layer, and forming a second barrier layer on the first barrier layer and on the sacrificial layer. The second barrier layer may include a portion formed on the sacrificial layer. The methods may also include forming a first insulating layer in the opening and protruding beyond a top surface of the portion of the second barrier layer on the sacrificial layer, a top surface of the first insulating layer being farther from the first barrier layer than the top surface of the portion of the second barrier layer, forming a redistribution structure including a redistribution layer and a second insulating layer on the first insulating layer and on the second barrier layer, mounting a semiconductor chip on the redistribution structure, attaching a second carrier onto the semiconductor chip and removing the first carrier, removing the first barrier layer, the sacrificial layer, and the second barrier layer to expose portions of the redistribution structure, and forming solder balls, respectively, on the portions of the redistribution structure.

    Package substrates, semiconductor packages having the same, and methods of fabricating the semiconductor packages
    7.
    发明授权
    Package substrates, semiconductor packages having the same, and methods of fabricating the semiconductor packages 有权
    封装衬底，具有其的半导体封装以及制造半导体封装的方法

    公开(公告)号：US08759221B2

    公开(公告)日：2014-06-24

    申请号：US13924817

    申请日：2013-06-24

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Jin-Woo Park ,  Hwan-Sik Lim ,  Eunchul Ahn

    IPC: H01L21/302

    CPC classification number: H01L21/50 ,  H01L21/563 ,  H01L23/48 ,  H01L23/58 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2924/00012

    Abstract: A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip.

    Abstract translation: 封装基板，具有该封装基板的半导体封装以及半导体封装的制造方法。 半导体封装包括半导体芯片，封装基板和模制层。 封装衬底提供安装有半导体芯片的区域。 模制层被配置成模制半导体芯片。 封装基板包括第一开口部分，该第一开口部分提供与半导体芯片电连接的开放区域，并且延伸超过半导体芯片的两侧以与半导体芯片电连接。

    Semiconductor package with dummy pattern not electrically connected to circuit pattern
    8.
    发明授权
    Semiconductor package with dummy pattern not electrically connected to circuit pattern 有权

    公开(公告)号：US11658131B2

    公开(公告)日：2023-05-23

    申请号：US17168337

    申请日：2021-02-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin-Woo Park ,  Un-Byoung Kang ,  Jong Ho Lee

    IPC: H01L23/14 ,  H01L23/00 ,  H01L23/498

    CPC classification number: H01L23/562 ,  H01L23/14 ,  H01L23/49816 ,  H01L24/14

    Abstract: A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.

Patent Agency Ranking