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公开(公告)号：US20130234101A1
公开(公告)日：2013-09-12
申请号：US13884331
申请日：2010-11-22
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L27/1157 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/66833 , H01L29/7926 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1616 , H01L45/1683
摘要： A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.
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公开(公告)号：US20120248399A1
公开(公告)日：2012-10-04
申请号：US13515435
申请日：2010-12-13
申请人： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikastsu Takaura
发明人： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikastsu Takaura
IPC分类号： H01L27/24
CPC分类号： H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
摘要翻译： 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。
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公开(公告)号：US08169819B2
公开(公告)日：2012-05-01
申请号：US12688886
申请日：2010-01-17
申请人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以配置三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。
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公开(公告)号：US20100032637A1
公开(公告)日：2010-02-11
申请号：US12434633
申请日：2009-05-02
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/1675 , Y10S438/90
摘要： Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.
摘要翻译： 本发明提供一种非易失性存储装置，其包括：配置有交叉点存储单元的相变存储器，其中由相变材料形成的存储元件和由二极管形成的选择元件组合。 存储单元配置有由相变材料形成的存储元件和由具有第一多晶硅膜，第二多晶硅膜和第三多晶硅膜的堆叠结构的二极管形成的选择元件。 存储单元布置在沿着第一方向延伸的多个第一金属布线的交点和沿着与第一方向正交的第二方向延伸的多个第三金属布线。 在相邻的选择元件之间和相邻的存储元件之间形成中间膜，并且在设置在相邻的存储元件之间的层间膜中形成空隙。
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公开(公告)号：US08866123B2
公开(公告)日：2014-10-21
申请号：US13884331
申请日：2010-11-22
IPC分类号： H01L47/00 , H01L45/00 , H01L29/792 , H01L27/24 , H01L29/66 , H01L27/115
CPC分类号： H01L27/2436 , H01L27/1157 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/66833 , H01L29/7926 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1616 , H01L45/1683
摘要： A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.
摘要翻译： 垂直链式存储器包括具有第一选择晶体管的两层选择晶体管，它们是以矩阵形式排列的垂直晶体管，第二选择晶体管是形成在各个第一选择晶体管上的垂直晶体管，以及多个存储单元串联连接 双层选择晶体管。 利用这种配置，防止相邻的选择晶体管被相应的共享栅极选择，可以独立地选择多个两层选择晶体管，并且防止非易失性存储装置的存储容量减小。
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公开(公告)号：US08772746B2
公开(公告)日：2014-07-08
申请号：US13349653
申请日：2012-01-13
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2454 , H01L27/2472 , H01L45/144 , H01L45/1675
摘要： A semiconductor memory device in which the cell area can be decreased and the minimum feature size is not restricted by the thickness of the material forming the memory cell. In a semiconductor memory device, a gate insulating film, a channel extending in a direction X, and a resistance change element extending in the direction X are formed successively above multiple word lines extending in a direction Y, and a portion of the channel and a portion of the resistance change element are disposed above each of the plurality of the word lines. Such configuration can decrease the cell area and ensure the degree of design freedom.
摘要翻译： 可以减小单元面积并且最小特征尺寸不受形成存储单元的材料的厚度的半导体存储器件。 在半导体存储器件中，连续地沿着Y方向延伸的多个字线形成栅极绝缘膜，沿X方向延伸的沟道和沿X方向延伸的电阻变化元件，并且沟道的一部分和 电阻变化元件的一部分设置在多条字线的上方。 这样的配置可以减小单元面积并确保设计自由度。
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公开(公告)号：US08642988B2
公开(公告)日：2014-02-04
申请号：US13588112
申请日：2012-08-17
IPC分类号： H01L29/02
CPC分类号： H01L45/144 , G11C13/0004 , G11C2213/71 , G11C2213/74 , G11C2213/75 , G11C2213/78 , H01L27/2409 , H01L27/2481 , H01L45/06
摘要： A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.
摘要翻译： 非易失性存储器件包括：沿衬底的主表面延伸的第一线; 提供在第一行之上的堆栈; 在堆叠之上形成第二线; 设置在所述第一和第二线相交的选择元件，所述选择元件适于在垂直于所述主表面的方向上传递电流; 沿着所述堆叠的侧表面设置的第二绝缘膜; 沿所述第二绝缘膜设置的沟道层; 沿着沟道层提供的粘合层; 以及沿着粘合层设置的可变电阻材料层，其中第一和第二线经由选择元件和沟道层电连接，通过沟道层和可变电阻材料层之间的粘合层的接触电阻低，并且 粘合层的电阻相对于沟道层的延伸方向高。
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公开(公告)号：US08132063B2
公开(公告)日：2012-03-06
申请号：US13191442
申请日：2011-07-26
申请人： Motoyasu Terao , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
发明人： Motoyasu Terao , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
IPC分类号： G11C29/00
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C29/028 , G11C29/50 , G11C29/50008 , G11C2013/0054 , G11C2213/72
摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.
摘要翻译： 为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。
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19.发明申请公开(公告)号：US20110284817A1
公开(公告)日：2011-11-24
申请号：US13109985
申请日：2011-05-17
CPC分类号： H01L27/2481 , H01L27/1021 , H01L27/2409 , H01L27/2436 , H01L27/2472
摘要： In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.
摘要翻译： 在非易失性半导体存储器件中，提供了一种通过减小作为选择元件的多晶硅二极管的截止电流来减小器件厚度来促进微细加工的技术。 形成以低浓度掺杂有杂质并作为电阻可变存储器的选择元件的多晶硅二极管的电场弛豫层的多晶硅层，以被分成两层或多层，例如多晶硅 层。 以这种方式抑制电场弛豫层中的n型多晶硅层和p型多晶硅层之间的晶粒边界完全透过，从而防止产生流过的漏电流 在不增加多晶硅二极管的高度的情况下施加反偏压的晶粒边界。
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公开(公告)号：US09099177B2
公开(公告)日：2015-08-04
申请号：US14124725
申请日：2011-06-10
CPC分类号： G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/71 , G11C2213/75 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.
摘要翻译： 为了提供适合于小型化并允许接触电阻降低的半导体存储器件，存储器阵列（MA）的布线结构如下形成。 也就是说，字线（2）和位线（3）彼此并行扩展，每条字线与另一个字线捆绑，每个位线与另一个位线捆绑，并且两个位线 在相应的捆绑的两条字线上垂直形成的电路分离。 这样的配置使得可以：在电线的捆扎部分（MLC）处形成较大的接触; 并降低适于小型化的存储器阵列中的接触电阻。
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