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    Fast locking CDR for burst mode
    11.
    发明授权
    Fast locking CDR for burst mode 有权
    快速锁定CDR用于突发模式

    公开(公告)号：US09209960B1

    公开(公告)日：2015-12-08

    申请号：US14550576

    申请日：2014-11-21

    Applicant: Xilinx, Inc.

    Inventor： Caleb S. Leung ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yu Xu ,  Yohan Frans ,  Kun-Yung Chang

    IPC: H04L7/00

    CPC classification number: H04L7/0337 ,  H04L7/0025

    Abstract: A method relates generally to a receiver. In such a method, a check of a clock and data recovery block of the receiver for a metastable state is performed. A phase input to a phase interpolator of the receiver is changed to cause the clock and data recovery block of the receiver to exit the metastable state within a time limit. To check for the metastable state, a phase difference in received data is determined, and the phase difference is determined to be less than a threshold for the clock and data recovery block being in the metastable state.

    Abstract translation: 一种方法一般涉及接收机。 在这种方法中，执行用于亚稳态的接收机的时钟和数据恢复块的检查。 接收机的相位内插器的相位输入被改变，以使接收器的时钟和数据恢复块在时间限制内退出亚稳态。 为了检查亚稳态，确定接收数据中的相位差，并且确定相位差小于时钟和数据恢复块处于亚稳态的阈值。

    Clock phase aligner for high speed data serializers
    13.
    发明授权
    Clock phase aligner for high speed data serializers 有权

    公开(公告)号：US10712770B1

    公开(公告)日：2020-07-14

    申请号：US16042785

    申请日：2018-07-23

    Applicant: Xilinx, Inc.

    Inventor： Ping-Chuan Chiang ,  Kee Hian Tan ,  Arianne B. Roldan ,  Nakul Narang ,  Yipeng Wang ,  Yohan Frans ,  Kun-Yung Chang

    IPC: G06F1/12 ,  G06F1/10 ,  H03K19/018 ,  H04J3/06 ,  G06F13/16 ,  G11C7/22

    Abstract: Apparatus and associated methods relate to a high-speed data serializer with a clock calibration module including a main multiplexer (MMUX), a replicated multiplexer (RMUX), a duty cycle calibration module (DCC), and a set of adjustable delay lines (ADLs), the ADLs generating calibrated clocks from a set of system clocks, the DCC sensing duty cycle and phase of the calibrated clocks. In an illustrative example, the DCC may generate error signals indicative of deviation from an expected duty cycle using low-pass filters. The error signals control the ADLs, which may provide continuous corrections to the calibrated clocks, for example. The MMUX and RMUX may receive the calibrated clocks, the RMUX generating a duty cycle indicating clock-to-data phasing, the MMUX providing live data multiplexing, for example. Various multiplexer calibration schemes may reduce jitter, which may facilitate increased data rates associated with high-speed serial data streams.

    Thermal calibration of a ring modulator
    14.
    发明授权
    Thermal calibration of a ring modulator 有权

    公开(公告)号：US10651933B1

    公开(公告)日：2020-05-12

    申请号：US16421425

    申请日：2019-05-23

    Applicant: Xilinx, Inc.

    Inventor： Ping-Chuan Chiang ,  Kee Hian Tan ,  Gourav Modi ,  Nakul Narang ,  Haibing Zhao ,  Yohan Frans

    IPC: H04B10/079 ,  G02F1/025 ,  G02F1/015

    Abstract: Systems and methods for calibrating a ring modulator are described. A system may include a controller configured to provide a first test signal to the ring modulator, determine a first candidate temperature control signal for a heater of the ring modulator when the first test signal is provided to the ring modulator, determine a first optical swing of an optical signal at a drop port of the ring modulator, determine a second candidate temperature control signal for the heater when the first test signal is provided to the ring modulator, determine a second optical swing of an optical signal at the drop port, select an optimal optical swing from the first optical swing and the second optical swing, and select one of the first candidate temperature control signal or the second candidate temperature control signal based on the optimal optical swing selected.

    System and method for transmitter
    15.
    发明授权
    System and method for transmitter 有权

    公开(公告)号：US10348290B1

    公开(公告)日：2019-07-09

    申请号：US15472080

    申请日：2017-03-28

    Applicant: Xilinx, Inc.

    Inventor： Hongtao Zhang ,  Yohan Frans

    IPC: H04B1/04 ,  H03K17/14 ,  H03K19/177

    Abstract: A transmitter includes a predriver circuit configured to perform a first equalization process to compensate jitter caused by the predriver circuit. The predriver circuit includes a first path having a first driving strength and configured to generate a first path output signal by applying a first delay to a predriver input signal. The predriver circuit includes a second path having a second driving strength less than the first driving strength and configured to generate a second path output signal by applying a second delay to the predriver input signal. A summing node is configured to combine the first path output signal and the second path output signal to provide a summing node output signal. A driver circuit coupled to the predriver circuit is configured to generate a driver output signal based on the summing node output signal and drive the driver output signal to a receiver through a channel.

    ADC BASED RECEIVER
    16.
    发明申请
    ADC BASED RECEIVER 审中-公开

    公开(公告)号：US20180287837A1

    公开(公告)日：2018-10-04

    申请号：US15471364

    申请日：2017-03-28

    Applicant: Xilinx, Inc.

    Inventor： Hongtao Zhang ,  Yohan Frans ,  Geoffrey Zhang

    IPC: H04L27/01 ,  H04B1/06

    CPC classification number: H04L27/01 ,  H03M1/182 ,  H03M1/361 ,  H04B1/06 ,  H04B2203/5425 ,  H04L25/063 ,  H04Q2213/03

    Abstract: A receiver includes: an automatic gain controller (AGC) configured to receive an analog signal; an analog-to-digital converter (ADC) configured to receive an output from the AGC and to output a digitized signal, wherein a most significant bit of the digitized signal corresponds to a sliced data, and a least significant bit of the digitized signal corresponds to an error signal; and an adaptation unit configured to control the AGC, the ADC, or both the AGC and the ADC, based at least in part on the digitized signal to achieve a desired data digitization and data slicing.

    Impedance and swing control for voltage-mode driver
    17.
    发明授权
    Impedance and swing control for voltage-mode driver 有权

    公开(公告)号：US10033412B2

    公开(公告)日：2018-07-24

    申请号：US15837791

    申请日：2017-12-11

    Applicant: Xilinx, Inc.

    Inventor： Siok Wei Lim ,  Kok Lim Chan ,  Kee Hian Tan ,  Hongyuan Zhao ,  Chin Yang Koay ,  Yohan Frans ,  Kun-Yung Chang

    IPC: H03K17/687 ,  H04B1/04 ,  H03M9/00 ,  H02M3/158

    Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

    OFFSET INSENSITIVE QUADRATURE CLOCK ERROR CORRECTION AND DUTY CYCLE CALIBRATION FOR HIGH-SPEED CLOCKING
    18.
    发明申请
    OFFSET INSENSITIVE QUADRATURE CLOCK ERROR CORRECTION AND DUTY CYCLE CALIBRATION FOR HIGH-SPEED CLOCKING 有权
    偏移时钟错误校正和占空比校准用于高速时钟

    公开(公告)号：US20170033774A1

    公开(公告)日：2017-02-02

    申请号：US14814401

    申请日：2015-07-30

    Applicant: Xilinx, Inc.

    Inventor： Hiva Hedayati ,  Yohan Frans

    IPC: H03K3/017

    CPC classification number: H03K3/017 ,  G06F1/04 ,  H03K5/1565

    Abstract: Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the detection circuitry, the stored charge compensates for the device mismatch, improving the accuracy of the detection circuit. The sampling operation is used for duty cycle distortion detection as well. Specifically, a common mode voltage is applied to sampling capacitors, which effectively zeroes the voltage differential between the sampling capacitors, compensating for offset that might exist due to operation of other components of the detection circuit. A digital value is used by a feedback algorithm to correct the clock distortion.

    Abstract translation: 校正时钟失真的技术。 这些技术包括使用用于检测和校正占空比失真和正交时钟相位失真的电路。 对于相位检测，通过使用采样操作使得检测电路变得更简单和更准确，其中检测电路中的器件失配通过采样电容器两端的理想时钟信号的采样电荷来考虑。 当用检测电路执行相位检测时，存储的电荷补偿器件不匹配，提高检测电路的精度。 采样操作也用于占空比失真检测。 具体地说，共模电压被施加到采样电容器，这样使得采样电容器之间的电压差有效地被归零，从而补偿由于检测电路的其它部件的操作而可能存在的偏移。 反馈算法使用数字值来校正时钟失真。

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