公开(公告)号：US11824534B2

公开(公告)日：2023-11-21

申请号：US17455195

申请日：2021-11-16

Applicant: XILINX, INC.

Inventor： Nakul Narang ,  Siok Wei Lim ,  Luhui Chen ,  Yipeng Wang ,  Kee Hian Tan

IPC: H04L25/02 ,  H03K19/17736 ,  G06F13/10 ,  H03K19/17788 ,  H04J3/04

CPC classification number: H03K19/17744 ,  G06F13/102 ,  H03K19/17788 ,  H04J3/047 ,  H04L25/0272

Abstract: A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.

公开(公告)号：US11146262B1

公开(公告)日：2021-10-12

申请号：US16930785

申请日：2020-07-16

Applicant: Xilinx, Inc.

Inventor： Yipeng Wang ,  Kee Hian Tan

IPC: H03K3/00 ,  H03K17/16 ,  H03K19/003 ,  H03K17/14

Abstract: A reference voltage generator is disclosed. The reference voltage generator may include an operational transconductance amplifier (OTA), a bias generator, a first flipped voltage follower, a bias filter, a control signal filter, and a second flipped voltage follower. The OTA and the first flipped voltage follower may generate a control signal based on a reference voltage and a bias voltage from the bias generator. The bias filter may filter the bias voltage and the control signal filter may filter the control signal. The second flipped voltage follower may generate the output voltage based on the filtered bias voltage and the filtered control signal.

公开(公告)号：US10530375B1

公开(公告)日：2020-01-07

申请号：US16122761

申请日：2018-09-05

Applicant: Xilinx, Inc.

Inventor： Yipeng Wang ,  Kee Hian Tan ,  Stanley Y. Chen ,  Yohan Frans

IPC: H03B19/12 ,  H03L7/197 ,  H03L7/193

Abstract: A frequency divider circuit (200) includes a frequency sub-divider (201) to provide a frequency divided clock, a delay circuit (250) configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit (202) configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.

公开(公告)号：US10712770B1

公开(公告)日：2020-07-14

申请号：US16042785

申请日：2018-07-23

Applicant: Xilinx, Inc.

Inventor： Ping-Chuan Chiang ,  Kee Hian Tan ,  Arianne B. Roldan ,  Nakul Narang ,  Yipeng Wang ,  Yohan Frans ,  Kun-Yung Chang

IPC: G06F1/12 ,  G06F1/10 ,  H03K19/018 ,  H04J3/06 ,  G06F13/16 ,  G11C7/22

Abstract: Apparatus and associated methods relate to a high-speed data serializer with a clock calibration module including a main multiplexer (MMUX), a replicated multiplexer (RMUX), a duty cycle calibration module (DCC), and a set of adjustable delay lines (ADLs), the ADLs generating calibrated clocks from a set of system clocks, the DCC sensing duty cycle and phase of the calibrated clocks. In an illustrative example, the DCC may generate error signals indicative of deviation from an expected duty cycle using low-pass filters. The error signals control the ADLs, which may provide continuous corrections to the calibrated clocks, for example. The MMUX and RMUX may receive the calibrated clocks, the RMUX generating a duty cycle indicating clock-to-data phasing, the MMUX providing live data multiplexing, for example. Various multiplexer calibration schemes may reduce jitter, which may facilitate increased data rates associated with high-speed serial data streams.

公开(公告)号：US10598852B1

公开(公告)日：2020-03-24

申请号：US16425009

申请日：2019-05-29

Applicant: Xilinx, Inc.

Inventor： Hai bing Zhao ,  Kee Hian Tan ,  Ping-Chuan Chiang ,  Yipeng Wang ,  Yohan Frans

IPC: G09G3/36 ,  G02B6/12 ,  H03M1/50 ,  G02B6/42

Abstract: A data driver includes pre-driver circuitry coupled to a digital-to-analog converter (DAC) via a plurality of bit lines. The pre-driver circuitry is configured to receive a plurality of first voltages corresponding to respective bits of a digital codeword. Each of the first voltages may have one of a first voltage value or a ground potential based on a value of the corresponding bit. The pre-driver circuitry is further configured to drive a plurality of second voltages onto the plurality of bit lines, respectively, by switchably coupling each of the bit lines to ground or a voltage rail based at least in part on the voltage values of the plurality of first voltages. The voltage rail provides a second voltage value that is greater than the first voltage value. The DAC converts the plurality of second voltages to an electrical signal which is an analog representation of the digital codeword.