公开(公告)号：US20190123728A1

公开(公告)日：2019-04-25

申请号：US15788617

申请日：2017-10-19

Applicant: Xilinx, Inc.

Inventor： Hai Bing Zhao ,  Kee Hian Tan ,  Ping-Chuan Chiang ,  Yohan Frans

IPC: H03K5/156 ,  H04L7/033 ,  H04L7/00

Abstract: A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.

公开(公告)号：US10598852B1

公开(公告)日：2020-03-24

申请号：US16425009

申请日：2019-05-29

Applicant: Xilinx, Inc.

Inventor： Hai bing Zhao ,  Kee Hian Tan ,  Ping-Chuan Chiang ,  Yipeng Wang ,  Yohan Frans

IPC: G09G3/36 ,  G02B6/12 ,  H03M1/50 ,  G02B6/42

Abstract: A data driver includes pre-driver circuitry coupled to a digital-to-analog converter (DAC) via a plurality of bit lines. The pre-driver circuitry is configured to receive a plurality of first voltages corresponding to respective bits of a digital codeword. Each of the first voltages may have one of a first voltage value or a ground potential based on a value of the corresponding bit. The pre-driver circuitry is further configured to drive a plurality of second voltages onto the plurality of bit lines, respectively, by switchably coupling each of the bit lines to ground or a voltage rail based at least in part on the voltage values of the plurality of first voltages. The voltage rail provides a second voltage value that is greater than the first voltage value. The DAC converts the plurality of second voltages to an electrical signal which is an analog representation of the digital codeword.

公开(公告)号：US10680592B2

公开(公告)日：2020-06-09

申请号：US15788617

申请日：2017-10-19

Applicant: Xilinx, Inc.

Inventor： Hai Bing Zhao ,  Kee Hian Tan ,  Ping-Chuan Chiang ,  Yohan Frans

IPC: H04L7/00 ,  H04L7/033 ,  H03K5/156

Abstract: A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.

公开(公告)号：US10712770B1

公开(公告)日：2020-07-14

申请号：US16042785

申请日：2018-07-23

Applicant: Xilinx, Inc.

Inventor： Ping-Chuan Chiang ,  Kee Hian Tan ,  Arianne B. Roldan ,  Nakul Narang ,  Yipeng Wang ,  Yohan Frans ,  Kun-Yung Chang

IPC: G06F1/12 ,  G06F1/10 ,  H03K19/018 ,  H04J3/06 ,  G06F13/16 ,  G11C7/22

Abstract: Apparatus and associated methods relate to a high-speed data serializer with a clock calibration module including a main multiplexer (MMUX), a replicated multiplexer (RMUX), a duty cycle calibration module (DCC), and a set of adjustable delay lines (ADLs), the ADLs generating calibrated clocks from a set of system clocks, the DCC sensing duty cycle and phase of the calibrated clocks. In an illustrative example, the DCC may generate error signals indicative of deviation from an expected duty cycle using low-pass filters. The error signals control the ADLs, which may provide continuous corrections to the calibrated clocks, for example. The MMUX and RMUX may receive the calibrated clocks, the RMUX generating a duty cycle indicating clock-to-data phasing, the MMUX providing live data multiplexing, for example. Various multiplexer calibration schemes may reduce jitter, which may facilitate increased data rates associated with high-speed serial data streams.

公开(公告)号：US10651933B1

公开(公告)日：2020-05-12

申请号：US16421425

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Ping-Chuan Chiang ,  Kee Hian Tan ,  Gourav Modi ,  Nakul Narang ,  Haibing Zhao ,  Yohan Frans

IPC: H04B10/079 ,  G02F1/025 ,  G02F1/015

Abstract: Systems and methods for calibrating a ring modulator are described. A system may include a controller configured to provide a first test signal to the ring modulator, determine a first candidate temperature control signal for a heater of the ring modulator when the first test signal is provided to the ring modulator, determine a first optical swing of an optical signal at a drop port of the ring modulator, determine a second candidate temperature control signal for the heater when the first test signal is provided to the ring modulator, determine a second optical swing of an optical signal at the drop port, select an optimal optical swing from the first optical swing and the second optical swing, and select one of the first candidate temperature control signal or the second candidate temperature control signal based on the optimal optical swing selected.