公开(公告)号：US12072239B1

公开(公告)日：2024-08-27

申请号：US18128948

申请日：2023-03-30

申请人： XILINX, INC.

发明人： Zhaowen Wang ,  Mayank Raj ,  Chuan Xie ,  Sandeep Kumar ,  Muqseed Mohammad ,  Sukruth Pattanagiri Giriyappa ,  Stanley Y. Chen ,  Parag Upadhyaya ,  Yohan Frans

IPC分类号： G01J1/44 ,  G01J1/02 ,  H03F3/45

CPC分类号： G01J1/44 ,  G01J1/0252 ,  H03F3/45076 ,  G01J2001/444 ,  G01J2001/446

摘要： An integrated circuit (IC) device includes a controller circuitry having an input coupled to a photodiode of an optoelectronic circuitry and an output coupled to a heater of the optoelectronic circuitry, the controller circuitry configured to determine a center frequency of the optoelectronic circuitry based on a shape of an input signal received from the photodiode, and provide a heater signal to the heater based on the shape of the input signal and the center frequency of the optoelectronic circuitry.

公开(公告)号：US11190172B1

公开(公告)日：2021-11-30

申请号：US17031694

申请日：2020-09-24

申请人： XILINX, INC.

发明人： Mayank Raj ,  Parag Upadhyaya

IPC分类号： H03K19/0185 ,  H04B17/18 ,  H04B10/516 ,  H03K3/356

摘要： Examples described herein generally relate to integrated circuits that include a latch-based level shifter circuit with self-biasing. In an example, an integrated circuit includes first and second latches and an output stage circuit. Each of the first and second latches includes a bias circuit electrically connected to a respective latch node and configured to provide a bias voltage at the respective latch node, which is electrically coupled to a signal input node. The output stage circuit has first and second input nodes electrically connected to first and second output nodes of the first and second latches, respectively, and a third output node. The output stage circuit is configured to responsively pull up and pull down a voltage of the third output node in response to respective voltages of the first and second input nodes.

公开(公告)号：US11668874B1

公开(公告)日：2023-06-06

申请号：US17700077

申请日：2022-03-21

申请人： XILINX, INC.

发明人： Zhaoyin Daniel Wu ,  Chuan Xie ,  Mayank Raj ,  Parag Upadhyaya

IPC分类号： G02B6/12 ,  G02B6/293

CPC分类号： G02B6/12016 ,  G02B6/2938 ,  G02B6/29338 ,  G02B6/29395

摘要： Disclosed herein is an optical filter configured for wavelength division and multiplexing capable of transmitting and receiving signals. The optical filter includes an optical waveguide configured to receive at an input multiple signals with different wavelengths. The optical filter includes a plurality of channels coupled at different locations along a length of the optical waveguide. Each of the plurality of channels is configured to transmit a respective one of the multiple signals. A number of ring filter stages in a first channel of the plurality of channels that is closer to the input of the optical waveguide is greater than a second channel in the plurality of channels further away from the input of the optical waveguide.

公开(公告)号：US11107770B1

公开(公告)日：2021-08-31

申请号：US16454629

申请日：2019-06-27

申请人： XILINX, INC.

发明人： Suresh Ramalingam ,  Kun-Yung Chang ,  Yohan Frans ,  Chuan Xie ,  Mayank Raj

IPC分类号： H01L23/538 ,  H01L23/13 ,  H01L23/49 ,  H01L25/18 ,  G02B6/42 ,  H01L25/00 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

摘要： An improved chip package, and methods for fabricating the same are provided that utilize two tier packaging of an optical die and another die commonly disposed over a substrate. In one example, a chip package is provided that includes an optical die, a core die, and an electrical/optical interface die are all disposed over a common substrate. In one example, a first routing region is provided between the core and electrical/optical interface dies, a second routing region is provided between the electrical/optical interface die and the optical dies, and a third routing region is disposed between the substrate and the core and electrical/optical interface dies.

公开(公告)号：US09960844B1

公开(公告)日：2018-05-01

申请号：US15474588

申请日：2017-03-30

申请人： Xilinx, Inc.

发明人： Mayank Raj ,  Yohan Frans ,  Kun-Yung Chang

IPC分类号： H04B10/00 ,  H04B10/077 ,  H04B10/60

CPC分类号： H04B10/0775 ,  G01R31/2635 ,  H03K17/78 ,  H04B10/60

摘要： An example photodiode emulator circuit includes: a first current source circuit; first and second transistors having sources coupled together and coupled to an output of the first current source circuit, a drain of the second transistor coupled to a first node; a third transistor coupled between a drain of the first transistor and a replica load circuit; a second current source circuit coupled to the first node; a capacitor coupled between the first node and electrical ground; and a fourth transistor having a source coupled to the first node and a drain that supplies an output current.

公开(公告)号：US08928334B1

公开(公告)日：2015-01-06

申请号：US13722800

申请日：2012-12-20

申请人： Xilinx, Inc.

发明人： Mayank Raj ,  Didem Z. Turker Melek

IPC分类号： G01R29/26

CPC分类号： G01R29/26 ,  G01R31/31708

摘要： An apparatus relating to on-chip noise measurement is disclosed. In such an apparatus, an asynchronous comparator receives a first input and a second input to provide a digital output. A threshold voltage generator receives a first periodic signal and a second periodic signal to provide the second input as an analog voltage responsive to the first and second periodic signals. A sampling circuit is coupled to receive the digital output signal and a third periodic signal. The sampling circuit is configured to sample the digital output signal using the third periodic signal to provide a sampled signal of the digital output signal. A processor is coupled to receive a delay signal and the sampled signal to determine a noise measurement signal for the first input signal.

摘要翻译： 公开了一种与片上噪声测量相关的装置。 在这种装置中，异步比较器接收第一输入和第二输入以提供数字输出。 阈值电压发生器接收第一周期信号和第二周期信号，以响应于第一和第二周期信号将第二输入提供为模拟电压。 一个采样电路被耦合以接收数字输出信号和第三周期信号。 采样电路被配置为使用第三周期信号对数字输出信号进行采样，以提供数字输出信号的采样信号。 耦合处理器以接收延迟信号和采样信号以确定用于第一输入信号的噪声测量信号。

公开(公告)号：US12104949B1

公开(公告)日：2024-10-01

申请号：US18128397

申请日：2023-03-30

申请人： XILINX, INC.

发明人： Zhaowen Wang ,  Mayank Raj

IPC分类号： G01J1/44

CPC分类号： G01J1/44 ,  G01J2001/446

摘要： An integrated circuit (IC) device includes a controller circuitry having an input connected to a photodiode of an optoelectronic circuitry and an output connected to a biasing circuitry, the biasing circuitry having an input connected to the output of the controller circuitry, the controller circuitry configured to transmit a transimpedance control signal code to the biasing circuitry configured to cause the biasing circuitry to offset a DC current component of the output of the photodiode.

公开(公告)号：US10797658B1

公开(公告)日：2020-10-06

申请号：US16525258

申请日：2019-07-29

申请人： Xilinx, Inc.

发明人： Mayank Raj

IPC分类号： H04B10/00 ,  H03F3/08 ,  H01L23/522 ,  H01L23/64 ,  H03F1/34 ,  H04B10/25 ,  H04L25/03 ,  H04B10/61

摘要： An optical receiver circuit is disclosed, including a photodiode, an output terminal, a first amplifier stage, and an electrostatic discharge (ESD) protection circuit. The photodiode may generate a receiver current based on received optical signals. The first amplifier stage may be coupled between the photodiode and the output terminal and include a first inductor coupled between the photodiode and an input of a first inverter, and a second inductor coupled between the input of the first inverter and a first resistor. The first resistor may be coupled between the second inductor and an output of the first inverter. ESD protection circuit may be coupled to the input of the first inverter. The output terminal may generate an output signal based at least in part on the output of the first inverter.

公开(公告)号：US10367591B2

公开(公告)日：2019-07-30

申请号：US15862058

申请日：2018-01-04

申请人： Xilinx, Inc.

发明人： Mayank Raj

IPC分类号： H04B17/18 ,  H04B10/516

摘要： An optical driver is disclosed, including a PMOS pull-up circuit, an NMOS pull-down circuit, and an inductive circuit. The PMOS pull-up circuit may include a first terminal to receive a first input signal based on a received data signal, and a P output terminal coupled to the inductive circuit. The NMOS pull-down circuit may include a second input terminal to receive a second input signal based on the received data signal, and an N output terminal coupled to the inductive circuit. The inductive circuit may include an L output terminal to output an output signal, a P coil coupled between the P output terminal and the L output terminal, and an N coil coupled between the N output terminal and the L output terminal. The P coil may be configured to hide a parasitic capacitance associated with the PMOS pull-up circuit during a falling edge transition of the received data signal, and the N coil may be configured to hide a parasitic capacitance associated with the NMOS pull-down circuit during a rising edge transition of the received data signal.

公开(公告)号：US09954539B2

公开(公告)日：2018-04-24

申请号：US15206634

申请日：2016-07-11

申请人： Xilinx, Inc.

发明人： Jinyung Namkoong ,  Mayank Raj ,  Parag Upadhyaya ,  Vamshi Manthena ,  Catherine Hearne ,  Marc Erett

IPC分类号： H03L7/06 ,  H03L7/089 ,  H03M9/00

CPC分类号： H03L7/0891 ,  H03L7/0805 ,  H03L7/0995 ,  H03L7/24 ,  H03M9/00

摘要： A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.