公开(公告)号：US11769710B2

公开(公告)日：2023-09-26

申请号：US16833034

申请日：2020-03-27

申请人： XILINX, INC.

发明人： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Ken Chang ,  Mayank Raj ,  Chuan Xie ,  Yohan Frans

IPC分类号： H01L23/473 ,  H01L25/16 ,  H01L23/367 ,  H01L23/40

CPC分类号： H01L23/473 ,  H01L23/3675 ,  H01L25/167 ,  H01L2023/4062

摘要： Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.

公开(公告)号：US11245554B1

公开(公告)日：2022-02-08

申请号：US16903377

申请日：2020-06-17

申请人： XILINX, INC.

发明人： Hongtao Zhang ,  Winson Lin ,  Arianne Roldan ,  Yohan Frans ,  Geoff Zhang

IPC分类号： H04L25/03 ,  H03L7/089 ,  H04L27/01

摘要： An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.

公开(公告)号：US10749532B1

公开(公告)日：2020-08-18

申请号：US16291286

申请日：2019-03-04

申请人： Xilinx, Inc.

发明人： Mayank Raj ,  Didem Z. Turker Melek ,  Parag Upadhyaya ,  Yohan Frans ,  Kun-Yung Chang

IPC分类号： H03L1/02 ,  H03L7/093 ,  H03L7/099 ,  H03L7/07 ,  H03L7/10

摘要： A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.

公开(公告)号：US10404445B1

公开(公告)日：2019-09-03

申请号：US16026967

申请日：2018-07-03

申请人： Xilinx, Inc.

发明人： Hongtao Zhang ,  Jinyung NamKoong ,  Winson Lin ,  Yohan Frans ,  Geoffrey Zhang

IPC分类号： H03D3/24 ,  H04L7/00 ,  H04L7/033 ,  H03L7/081

摘要： A receiver circuit for receiving data is described. The receiver circuit comprises a phase detector configured to receive an input data signal; a frequency path circuit configured to receive an output of the phase detector; and a false lock detection circuit configured to receive the output of the phase detector and an output of the frequency path circuit; wherein the false lock detection circuit detects a false lock of the receiver circuit to the input data signal based upon an output of the phase detector and provides a frequency offset to the frequency path circuit. A method of receiving data is also described.

公开(公告)号：US20190123728A1

公开(公告)日：2019-04-25

申请号：US15788617

申请日：2017-10-19

申请人： Xilinx, Inc.

发明人： Hai Bing Zhao ,  Kee Hian Tan ,  Ping-Chuan Chiang ,  Yohan Frans

IPC分类号： H03K5/156 ,  H04L7/033 ,  H04L7/00

摘要： A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.

公开(公告)号：US12063129B2

公开(公告)日：2024-08-13

申请号：US17665477

申请日：2022-02-04

申请人： XILINX, INC.

发明人： Hongtao Zhang ,  Winson Lin ,  Arianne Roldan ,  Yohan Frans ,  Geoff Zhang

IPC分类号： H04L25/03 ,  H03L7/089 ,  H04L27/01

CPC分类号： H04L25/03057 ,  H03L7/0891 ,  H04L27/01 ,  H04L2025/0349

摘要： An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.

公开(公告)号：US11005572B1

公开(公告)日：2021-05-11

申请号：US17093399

申请日：2020-11-09

申请人： XILINX, INC.

发明人： Ping Chuan Chiang ,  Mayank Raj ,  Chuan Xie ,  Stanley Y. Chen ,  Sandeep Kumar ,  Sukruth Pattanagiri ,  Parag Upadhyaya ,  Yohan Frans

IPC分类号： H04B10/69 ,  H03L1/02 ,  H03L7/189

摘要： Examples described herein generally relate to a temperature-locked loop for optical elements. In an example, a device includes a controller and a digital-to-analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a slicer circuit, and a processor. The DCTS is configured to be coupled to a photodiode. An input node of the slicer circuit is coupled to an output node of the DCTS. The processor has an input node coupled to an output node of the slicer circuit. The DAC has an input node coupled to an output node of the processor and is configured to be coupled to a heater. The processor is configured to control (i) the DCTS to reduce a DC component of a signal on the output node of the DCTS and (ii) an output voltage on the output node of the DAC, both based on a signal output by the slicer circuit.

公开(公告)号：US20200287551A1

公开(公告)日：2020-09-10

申请号：US16291286

申请日：2019-03-04

申请人： Xilinx, Inc.

发明人： Mayank Raj ,  Didem Z. Turker Melek ,  Parag Upadhyaya ,  Yohan Frans ,  Kun-Yung Chang

IPC分类号： H03L1/02 ,  H03L7/099 ,  H03L7/093

摘要： A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.

公开(公告)号：US10680592B2

公开(公告)日：2020-06-09

申请号：US15788617

申请日：2017-10-19

申请人： Xilinx, Inc.

发明人： Hai Bing Zhao ,  Kee Hian Tan ,  Ping-Chuan Chiang ,  Yohan Frans

IPC分类号： H04L7/00 ,  H04L7/033 ,  H03K5/156

摘要： A quadrature clock correction (QCC) circuit includes: a first pair of clock correction circuits that output in-phase and anti-in-phase clock signals, respectively, of a four-phase clock signal; a second pair of clock correction circuits that output quadrature-phase and anti-quadrature-phase clock signals, respectively, of the four-phase clock signal; a detector circuit configured to detect duty cycle error and in-phase/quadrature-phase (IQ) phase mismatch in the four-phase clock signal; and a calibration circuit configured to supply a first pair of control signals to each the first pair of clock correction circuits, and a second pair of control signals to each of the second pair of clock correction circuits, to correct both the duty cycle error and the IQ phase mismatch based output of the detector circuit.

公开(公告)号：US20180041232A1

公开(公告)日：2018-02-08

申请号：US15227853

申请日：2016-08-03

申请人： Xilinx, Inc.

发明人： Siok Wei Lim ,  Kok Lim Chan ,  Kee Hian Tan ,  Hongyuan Zhao ,  Chin Yang Koay ,  Yohan Frans ,  Kun-Yung Chang

IPC分类号： H04B1/04 ,  H03M9/00 ,  H02M3/158 ,  H03K17/687

CPC分类号： H04B1/04 ,  H02M3/158 ,  H03K17/163 ,  H03K17/6872 ,  H03K19/0175 ,  H03M9/00

摘要： A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.