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公开(公告)号：US10484167B2
公开(公告)日：2019-11-19
申请号：US15920251
申请日：2018-03-13
Applicant: Xilinx, Inc.
Inventor： Yi Zhuang , Winson Lin , Jinyung Namkoong , Hsung Jai Im , Stanley Y. Chen
IPC: H04L7/00 , H04L7/033 , G06F1/06 , H03K19/0175 , H03K19/20
Abstract: A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.
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公开(公告)号：US12063129B2
公开(公告)日：2024-08-13
申请号：US17665477
申请日：2022-02-04
Applicant: XILINX, INC.
Inventor： Hongtao Zhang , Winson Lin , Arianne Roldan , Yohan Frans , Geoff Zhang
CPC classification number: H04L25/03057 , H03L7/0891 , H04L27/01 , H04L2025/0349
Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.
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公开(公告)号：US09755792B1
公开(公告)日：2017-09-05
申请号：US15149937
申请日：2016-05-09
Applicant: Xilinx, Inc.
Inventor： Winson Lin
CPC classification number: H04L1/244 , G06F7/582 , H04L25/03343 , H04L25/4917
Abstract: An apparatus and method relate generally to generation and checking of a quaternary pseudo random binary sequence (“QPRBS”). In an apparatus, there is a pseudo random binary sequence (“PRBS”) generator configured to receive a seed of a PRBS to be generated. A mask generator is configured to generate a mask output corresponding to the PRBS. The PRBS generator and the mask generator are both configured for sequential operation with respect to one another. A masking circuit is configured to receive the mask output and the PRBS to bitwise mask the PRBS with the mask output to generate the QPRBS.
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公开(公告)号：US10404408B1
公开(公告)日：2019-09-03
申请号：US15377780
申请日：2016-12-13
Applicant: Xilinx, Inc.
Inventor： Winson Lin , Hongtao Zhang , Yu Xu , Geoffrey Zhang
Abstract: An example method of capturing an error distribution data for a serial channel includes: receiving a signal from the serial channel at a receiver in an integrated circuit (IC), the signal encoding data using pulse amplitude modulation (PAM) scheme having more than two levels; determining a plurality of symbols from the signal, each of the plurality of symbols encoding a plurality of bits; comparing the plurality of symbols with a plurality of expected symbols to detect a plurality of symbol errors; generating the error distribution data by accumulating numbers of the plurality of symbol errors across a plurality of bins based error type; and transmitting the error distribution data from the receiver to a computing system for processing.
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公开(公告)号：US10256968B1
公开(公告)日：2019-04-09
申请号：US15660141
申请日：2017-07-26
Applicant: Xilinx, Inc.
Inventor： Zhaoyin D. Wu , Yu Xu , Winson Lin , Yohan Frans , Geoffrey Zhang
Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.
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Patent Agency Ranking
公开(公告)号：US10038545B1
公开(公告)日：2018-07-31
申请号：US15660397
申请日：2017-07-26
Applicant: Xilinx, Inc.
Inventor： Zhaoyin D. Wu , Winson Lin , Yu Xu , Geoffrey Zhang
CPC classification number: H04L7/0025 , H03L7/07 , H03L7/0807 , H03L7/0814 , H04L7/0004 , H04L7/0012 , H04L7/033 , H04L7/0334 , H04L7/0337 , H04L7/0338 , H04L43/028 , H04L43/16
Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.
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公开(公告)号：US11245554B1
公开(公告)日：2022-02-08
申请号：US16903377
申请日：2020-06-17
Applicant: XILINX, INC.
Inventor： Hongtao Zhang , Winson Lin , Arianne Roldan , Yohan Frans , Geoff Zhang
Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.
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公开(公告)号：US20190288830A1
公开(公告)日：2019-09-19
申请号：US15920251
申请日：2018-03-13
Applicant: Xilinx, Inc.
Inventor： Yi Zhuang , Winson Lin , Jinyung Namkoong , Hsung Jai Im , Stanley Y. Chen
IPC: H04L7/033 , H04L7/00 , H03K19/0175 , G06F1/06
Abstract: A circuit for receiving a signal in an integrated circuit is described. The circuit comprises a sampler configured to receive an input data signal, wherein the sampler generates sampled data and a recovered clock; a clock and data recovery circuit configured to receive the sampled data and the recovered clock and to generate a phase interpolator code; and a phase interpolator configured to receive the phase interpolator code; wherein the phase interpolator generates multiple phase interpolator control signals during a clock cycle based upon the phase interpolator code generated for the clock cycle.
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公开(公告)号：US10404445B1
公开(公告)日：2019-09-03
申请号：US16026967
申请日：2018-07-03
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Jinyung NamKoong , Winson Lin , Yohan Frans , Geoffrey Zhang
Abstract: A receiver circuit for receiving data is described. The receiver circuit comprises a phase detector configured to receive an input data signal; a frequency path circuit configured to receive an output of the phase detector; and a false lock detection circuit configured to receive the output of the phase detector and an output of the frequency path circuit; wherein the false lock detection circuit detects a false lock of the receiver circuit to the input data signal based upon an output of the phase detector and provides a frequency offset to the frequency path circuit. A method of receiving data is also described.
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公开(公告)号：US10291239B1
公开(公告)日：2019-05-14
申请号：US16000698
申请日：2018-06-05
Applicant: Xilinx, Inc.
Inventor： Zhaoyin D. Wu , Winson Lin , Parag Upadhyaya , Geoffrey Zhang , Kun-Yung Chang
Abstract: An example apparatus includes an input circuit including a first adder and a first multiplier, the first adder configured to level-shift an input signal by an amount and the first multiplier configured to multiply output of the adder by a factor. The apparatus further includes a multi-stage noise shaping (MASH) circuit having an input coupled to the first multiplier. The apparatus further includes an output circuit including a second multiplier and a second adder, the second multiplier configured to multiply output of the MASH circuit by a reciprocal of the factor and the second adder configured to level-shift output of the second multiplier by an inverse of the amount.
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