公开(公告)号：US11245554B1

公开(公告)日：2022-02-08

申请号：US16903377

申请日：2020-06-17

Applicant: XILINX, INC.

Inventor： Hongtao Zhang ,  Winson Lin ,  Arianne Roldan ,  Yohan Frans ,  Geoff Zhang

IPC: H04L25/03 ,  H03L7/089 ,  H04L27/01

Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.

公开(公告)号：US12063129B2

公开(公告)日：2024-08-13

申请号：US17665477

申请日：2022-02-04

Applicant: XILINX, INC.

Inventor： Hongtao Zhang ,  Winson Lin ,  Arianne Roldan ,  Yohan Frans ,  Geoff Zhang

IPC: H04L25/03 ,  H03L7/089 ,  H04L27/01

CPC classification number: H04L25/03057 ,  H03L7/0891 ,  H04L27/01 ,  H04L2025/0349

Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.