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公开(公告)号：US10742453B1
公开(公告)日：2020-08-11
申请号：US16283453
申请日：2019-02-22
Applicant: Xilinx, Inc.
Inventor： Min Wu , Hongtao Zhang , Yu Xu
IPC: H04L25/03
Abstract: An equalizer circuit including a filter, equalization circuitry, and a filter adaptation circuit. The filter is configured to produce a linearized signal based at least in part on a received input signal and a nonlinear transfer function. The equalization circuitry is configured to filter inter-symbol interference (ISI) and detect one or more data symbols in the linearized signal. The equalization circuitry is further configured to produce an error signal indicating an amount of error in the detected data symbols. The filter adaptation circuit is configured to dynamically adjust the nonlinear transfer function of the filter based at least in part on the error signal from the equalization circuitry.
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公开(公告)号：US09882795B1
公开(公告)日：2018-01-30
申请号：US14689327
申请日：2015-04-17
Applicant: Xilinx, Inc.
Inventor： Hongtao Zhang , Geoffrey Zhang , Yu Xu , Patrick Satarzadeh , Zhaoyin D. Wu
CPC classification number: H04L43/0811 , H04L7/0087 , H04L25/03057
Abstract: In an example, an apparatus for detecting signal loss on a serial communication channel coupled to a receiver includes an input, a detector, and an output circuit. The input is configured to receive decisions generated by sampling the serial communication channel using multiplexed decision paths in a decision feedback equalizer (DFE). The detector is coupled to the input and configured to monitor the decisions for at least one pattern generated by the multiplexed decision paths in response to absence of a serial data signal on the serial communication channel. The output circuit is coupled to the detector and configured to assert loss-of-signal in response detection of the at least one pattern by the detector.
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公开(公告)号：US09379720B1
公开(公告)日：2016-06-28
申请号：US14715280
申请日：2015-05-18
Applicant: Xilinx, Inc.
Inventor： Yu Xu , Santiago G. Asuncion , Tianqi Tang , Toan Pham , Kun-Yung Chang
CPC classification number: H04L7/0337
Abstract: Clock data recovery can be accomplished using a phase path circuit that is configured to receive a data signal and a clock signal. A phase detection circuit detects phase differences between the data signal and a plurality of clock signals and generates a phase adjustment signal based upon a majority voting of the detected phase differences. Speculative calculation circuits generate speculative phase selection signals. Selection circuits select, in response to the phase adjustment signal, from speculative phase selection signals to provide outputs of the phase path circuit.
Abstract translation: 可以使用被配置为接收数据信号和时钟信号的相位路径电路来实现时钟数据恢复。 相位检测电路检测数据信号和多个时钟信号之间的相位差，并且基于检测到的相位差的多数投票产生相位调整信号。 投机计算电路产生推测相位选择信号。 选择电路响应于相位调整信号从推测相位选择信号中选择以提供相位路径电路的输出。
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公开(公告)号：US09209960B1
公开(公告)日：2015-12-08
申请号：US14550576
申请日：2014-11-21
Applicant: Xilinx, Inc.
Inventor： Caleb S. Leung , Alan C. Wong , Christopher J. Borrelli , Yu Xu , Yohan Frans , Kun-Yung Chang
IPC: H04L7/00
CPC classification number: H04L7/0337 , H04L7/0025
Abstract: A method relates generally to a receiver. In such a method, a check of a clock and data recovery block of the receiver for a metastable state is performed. A phase input to a phase interpolator of the receiver is changed to cause the clock and data recovery block of the receiver to exit the metastable state within a time limit. To check for the metastable state, a phase difference in received data is determined, and the phase difference is determined to be less than a threshold for the clock and data recovery block being in the metastable state.
Abstract translation: 一种方法一般涉及接收机。 在这种方法中，执行用于亚稳态的接收机的时钟和数据恢复块的检查。 接收机的相位内插器的相位输入被改变，以使接收器的时钟和数据恢复块在时间限制内退出亚稳态。 为了检查亚稳态，确定接收数据中的相位差，并且确定相位差小于时钟和数据恢复块处于亚稳态的阈值。
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公开(公告)号：US10530561B1
公开(公告)日：2020-01-07
申请号：US16359921
申请日：2019-03-20
Applicant: Xilinx, Inc.
Inventor： Zao Liu , Yang Liu , Zhaoyin D. Wu , Geoffrey Zhang , Yu Xu , Alan C. Wong
Abstract: Apparatus and associated methods relate to using a high learning rate to speed up the training of a receiver and switching from a high learning rate to a low learning rate for fine tuning based on exponentially weighted moving average convergence. In an illustrative example, a selection circuit may switch the high learning rate to the low learning rate based on a comparison of a moving average difference en to a predetermined stability criteria T1 of the receiver. The moving average difference en may include an exponentially weighted moving average of a difference between two consecutive exponentially weighted moving averages of an operation parameter un of the signal communication channel. By using this method, the training time for the receiver may be advantageously reduced.
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Patent Agency Ranking
公开(公告)号：US10404408B1
公开(公告)日：2019-09-03
申请号：US15377780
申请日：2016-12-13
Applicant: Xilinx, Inc.
Inventor： Winson Lin , Hongtao Zhang , Yu Xu , Geoffrey Zhang
Abstract: An example method of capturing an error distribution data for a serial channel includes: receiving a signal from the serial channel at a receiver in an integrated circuit (IC), the signal encoding data using pulse amplitude modulation (PAM) scheme having more than two levels; determining a plurality of symbols from the signal, each of the plurality of symbols encoding a plurality of bits; comparing the plurality of symbols with a plurality of expected symbols to detect a plurality of symbol errors; generating the error distribution data by accumulating numbers of the plurality of symbol errors across a plurality of bins based error type; and transmitting the error distribution data from the receiver to a computing system for processing.
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公开(公告)号：US10256968B1
公开(公告)日：2019-04-09
申请号：US15660141
申请日：2017-07-26
Applicant: Xilinx, Inc.
Inventor： Zhaoyin D. Wu , Yu Xu , Winson Lin , Yohan Frans , Geoffrey Zhang
Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.
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公开(公告)号：US10038545B1
公开(公告)日：2018-07-31
申请号：US15660397
申请日：2017-07-26
Applicant: Xilinx, Inc.
Inventor： Zhaoyin D. Wu , Winson Lin , Yu Xu , Geoffrey Zhang
CPC classification number: H04L7/0025 , H03L7/07 , H03L7/0807 , H03L7/0814 , H04L7/0004 , H04L7/0012 , H04L7/033 , H04L7/0334 , H04L7/0337 , H04L7/0338 , H04L43/028 , H04L43/16
Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a frequency accumulator, and a sequencer circuit. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples, which are generated by sampling a first data signal from a receiver using a sampling clock. The frequency accumulator accumulates, using a frequency register, frequency offset information from the phase detect result signal to generate an accumulated total. The frequency offset information is associated with a frequency difference between a first reference clock of the receiver and a second reference clock associated with the first data signal. The accumulated total is stored in the frequency register and provided from the frequency register for updating the sampling clock. The sequencer circuit is configured to perform a reset operation to reset the accumulated total in the frequency register based on a sequence of sequence elements.
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9.发明授权Clock data recovery (CDR) phase walk scheme in a phase-interpolater-based transceiver system 有权在基于相位插值器的收发机系统中的时钟数据恢复（CDR）相位行进方案公开(公告)号：US09356775B1
公开(公告)日：2016-05-31
申请号：US14795169
申请日：2015-07-09
Applicant: Xilinx, Inc.
Inventor： Yu Xu , Cheng-Hsiang Hsieh , Yohan Frans , Kun-Yung Chang
CPC classification number: H04L7/041 , H04L7/0025 , H04L7/0087 , H04L7/033 , H04L7/0337
Abstract: Methods and apparatus are described for synchronously stepping at least one of a data phase interpolator (PI) code or a crossing PI code in a clock and data recovery (CDR) circuit until one or more preset criteria are satisfied. One example method generally includes determining that a condition has been met; based on the determination, stepping, in a CDR circuit, at least one of a data PI code or a crossing PI code for each cycle of a clock; stopping the stepping based on one or more criteria to generate a predetermined state of the data PI code and the crossing PI code, wherein the predetermined state comprises an offset between the data PI code and the crossing PI code; receiving a data stream; and performing clock and data recovery on the data stream based on the offset between the data PI code and the crossing PI code.
Abstract translation: 描述了用于在时钟和数据恢复（CDR）电路中同步地步进数据相位内插器（PI）代码或交叉PI代码中的至少一个的方法和装置，直到满足一个或多个预设标准。 一个示例性方法通常包括确定已经满足条件; 基于所述确定，在CDR电路中步进每个时钟周期的数据PI代码或交叉PI代码中的至少一个; 基于一个或多个标准停止步进以产生数据PI代码和交叉PI代码的预定状态，其中预定状态包括数据PI代码和交叉PI代码之间的偏移量; 接收数据流; 并且基于数据PI代码和交叉PI代码之间的偏移在数据流上执行时钟和数据恢复。
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公开(公告)号：US09960902B1
公开(公告)日：2018-05-01
申请号：US15380653
申请日：2016-12-15
Applicant: Xilinx, Inc.
Inventor： Winson Lin , Yu Xu , Caleb S. Leung , Alan C. Wong , Christopher J. Borrelli , Yohan Frans , Kun-Yung Chang
CPC classification number: H04L1/205 , H03L7/0814 , H04L7/0037 , H04L7/033 , H04L7/0337
Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.
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