公开(公告)号：US09379720B1

公开(公告)日：2016-06-28

申请号：US14715280

申请日：2015-05-18

Applicant: Xilinx, Inc.

Inventor： Yu Xu ,  Santiago G. Asuncion ,  Tianqi Tang ,  Toan Pham ,  Kun-Yung Chang

IPC: H03D3/24 ,  H03L7/087 ,  H04L7/04

CPC classification number: H04L7/0337

Abstract: Clock data recovery can be accomplished using a phase path circuit that is configured to receive a data signal and a clock signal. A phase detection circuit detects phase differences between the data signal and a plurality of clock signals and generates a phase adjustment signal based upon a majority voting of the detected phase differences. Speculative calculation circuits generate speculative phase selection signals. Selection circuits select, in response to the phase adjustment signal, from speculative phase selection signals to provide outputs of the phase path circuit.

Abstract translation: 可以使用被配置为接收数据信号和时钟信号的相位路径电路来实现时钟数据恢复。 相位检测电路检测数据信号和多个时钟信号之间的相位差，并且基于检测到的相位差的多数投票产生相位调整信号。 投机计算电路产生推测相位选择信号。 选择电路响应于相位调整信号从推测相位选择信号中选择以提供相位路径电路的输出。