公开(公告)号：US10749729B1

公开(公告)日：2020-08-18

申请号：US16424328

申请日：2019-05-28

Applicant: Xilinx, Inc.

Inventor： Alan C. Wong ,  Hong Sik Ahn ,  Edward Lee ,  Christopher J. Borrelli

IPC: H04L27/12 ,  H04B1/20 ,  H04L27/38 ,  H03G3/30 ,  H04B1/16 ,  H04L25/03

Abstract: A circuit includes an AGC adaptation circuit configured to receive a first signal generated based on an AGC output signal from an AGC circuit. The AGC circuit applies an AGC gain to an AGC input signal to generate the AGC output signal. The AGC adaptation circuit determines an observed value of the first signal, and determines a AGC adaptation step size based on the observed value and a predetermined target value associated with the first signal. The AGC adaptation circuit provides a second signal to adjust the AGC gain of the AGC circuit using the AGC adaptation step size.

公开(公告)号：US10812089B2

公开(公告)日：2020-10-20

申请号：US16357169

申请日：2019-03-18

Applicant: Xilinx, Inc.

Inventor： Caleb S. Leung ,  Edward Lee ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans

IPC: H03L7/099 ,  H03K19/177 ,  H03L7/08

Abstract: Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.

公开(公告)号：US09065601B1

公开(公告)日：2015-06-23

申请号：US13842604

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Michael O. Jenkins ,  Cheng-Hsiang Hsieh ,  Christopher J. Borrelli

IPC: H04L7/04 ,  H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0337 ,  H03L7/0812 ,  H03L7/093 ,  H04L7/0025 ,  H04L7/033

Abstract: A receiver in an integrated circuit device is described. The circuit comprises a receiver having a clock and data recovery circuit coupled to receive data signals modulated with a transmitter clock signal; and a clock generator coupled to receive an output of the clock and data recovery circuit, the clock generator providing a modulated reference clock to the receiver, based upon a reference clock signal which is independent of the transmitter clock signal; wherein the modulated reference clock provided to the receiver is synchronized with the transmitter clock signal. A method of receiving data in an integrated circuit is also described.

Abstract translation: 描述了集成电路器件中的接收器。 该电路包括具有时钟和数据恢复电路的接收器，该时钟和数据恢复电路被耦合以接收用发射机时钟信号调制的数据信号; 以及时钟发生器，其耦合以接收所述时钟和数据恢复电路的输出，所述时钟发生器基于独立于所述发射机时钟信号的参考时钟信号向所述接收机提供调制参考时钟; 其中提供给接收机的调制参考时钟与发射机时钟信号同步。 还描述了在集成电路中接收数据的方法。

公开(公告)号：US11038768B1

公开(公告)日：2021-06-15

申请号：US15267002

申请日：2016-09-15

Applicant: Xilinx, Inc.

Inventor： Ivan O. Madrigal ,  Michael O. Jenkins ,  Hong S. Ahn ,  Murtuza Z. Cutleriwala ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans ,  Geoffrey Zhang ,  Hongtao Zhang

IPC: H04L25/03 ,  H04L12/24 ,  G06F30/331

Abstract: A method relates generally to comparison of a communications system modelled with a behavioral model and implemented with a circuit realization. In this method, operation of the communications system is simulated with the behavioral model on a computing device to obtain a first pulse response. The simulating includes first equalizing first data with a first equalizer of the behavioral model to obtain the first pulse response. The circuit realization is operated to obtain a second pulse response. The operating includes: second equalizing second data corresponding to the first data with a second equalizer of the circuit realization to obtain the second pulse response. The second pulse response from the circuit realization is loaded to memory of the computing device. The first pulse is loaded to the memory of the computing device. The first pulse response and the second pulse response are compared with one another by the computing device.

公开(公告)号：US09800438B1

公开(公告)日：2017-10-24

申请号：US15333505

申请日：2016-10-25

Applicant: Xilinx, Inc.

Inventor： Hongtao Zhang ,  Zhaoyin D. Wu ,  Christopher J. Borrelli ,  Geoffrey Zhang

IPC: H04L7/00 ,  H04L25/03 ,  H04L12/26

CPC classification number: H04L25/03885 ,  G01R31/02 ,  G01R31/44 ,  H04L7/0025 ,  H04L7/0087 ,  H04L25/03273

Abstract: An example method of performing an eye-scan in a receiver includes: generating digital samples from an analog signal input to the receiver based on a sampling clock, the sampling clock phase-shifted with respect to a reference clock based on a phase interpolator (PI) code; equalizing the digital samples based on first equalization parameters of a plurality of equalization parameters of the receiver; adapting the plurality of equalization parameters and performing clock recovery based on the digital samples to generate the PI code; and performing a plurality of cycles of locking the plurality of equalization parameters, suspending phase detection in the clock recovery, offsetting the PI code, collecting an output of the receiver, resuming the phase detection in the clock recovery, and unlocking the equalization parameters to perform the eye scan.

公开(公告)号：US09209960B1

公开(公告)日：2015-12-08

申请号：US14550576

申请日：2014-11-21

Applicant: Xilinx, Inc.

Inventor： Caleb S. Leung ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yu Xu ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04L7/00

CPC classification number: H04L7/0337 ,  H04L7/0025

Abstract: A method relates generally to a receiver. In such a method, a check of a clock and data recovery block of the receiver for a metastable state is performed. A phase input to a phase interpolator of the receiver is changed to cause the clock and data recovery block of the receiver to exit the metastable state within a time limit. To check for the metastable state, a phase difference in received data is determined, and the phase difference is determined to be less than a threshold for the clock and data recovery block being in the metastable state.

Abstract translation: 一种方法一般涉及接收机。 在这种方法中，执行用于亚稳态的接收机的时钟和数据恢复块的检查。 接收机的相位内插器的相位输入被改变，以使接收器的时钟和数据恢复块在时间限制内退出亚稳态。 为了检查亚稳态，确定接收数据中的相位差，并且确定相位差小于时钟和数据恢复块处于亚稳态的阈值。

公开(公告)号：US20200304130A1

公开(公告)日：2020-09-24

申请号：US16357169

申请日：2019-03-18

Applicant: Xilinx, Inc.

Inventor： Caleb S. Leung ,  Edward Lee ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans

IPC: H03L7/099 ,  H03L7/08 ,  H03K19/177

Abstract: Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.

公开(公告)号：US09960902B1

公开(公告)日：2018-05-01

申请号：US15380653

申请日：2016-12-15

Applicant: Xilinx, Inc.

Inventor： Winson Lin ,  Yu Xu ,  Caleb S. Leung ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04L7/00 ,  H04L1/20

CPC classification number: H04L1/205 ,  H03L7/0814 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0337

Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

公开(公告)号：US09882703B1

公开(公告)日：2018-01-30

申请号：US15346434

申请日：2016-11-08

Applicant: Xilinx, Inc.

Inventor： Yu Xu ,  Winson Lin ,  Caleb S. Leung ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans ,  Kun-Yung Chang

IPC: H03D3/24 ,  H04L7/00 ,  H04L12/26 ,  H04L7/033

CPC classification number: H04L43/16 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033 ,  H04L25/03 ,  H04L43/028

Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver; generating a phase detect result signal in response to phase detection of the data samples and the crossing samples; filtering the phase detect result signal to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code; determining an average phase detect result from the phase detect result signal; and adjusting the phase interpolator code in response to the average phase detect result being less than a threshold value.

公开(公告)号：US09148192B1

公开(公告)日：2015-09-29

申请号：US13962468

申请日：2013-08-08

Applicant: Xilinx, Inc.

Inventor： Alan C. Wong ,  Christopher J. Borrelli ,  Loren Jones ,  Seu Wah Low ,  Parag Upadhyaya ,  Robert M. Ondris ,  Sarosh I. Azad

IPC: H04B1/40

CPC classification number: H04L25/14

Abstract: An apparatus relating generally to a transmitter-side of a transceiver or a transmitter used to provide a clock signal is disclosed. In this apparatus, a first signal source is to provide a first periodic signal. A second signal source is to provide a second periodic signal. A first multiplexer is coupled to receive the first periodic signal and the second periodic signal to provide a selected one thereof as a first selected output. A phase interpolator is coupled to the first multiplexer to receive the first selected output. The phase interpolator includes a second multiplexer. The second multiplexer is coupled to receive the first selected output and a phase-interpolated version of the first selected output to output a selected one thereof as a second selected output. A divider is coupled to the second multiplexer to receive the second selected output to provide the clock signal.

Abstract translation: 公开了一种与用于提供时钟信号的收发机或发射机的发射机侧有关的装置。 在该装置中，第一信号源是提供第一周期信号。 第二信号源是提供第二周期信号。 第一多路复用器被耦合以接收第一周期性信号和第二周期信号，以将其选定的一个作为第一选择输出。 相位插值器耦合到第一多路复用器以接收第一选择的输出。 相位插值器包括第二多路复用器。 第二多路复用器被耦合以接收第一选择输出和第一选择输出的相位插值版本，以将其选定的一个输出作为第二选择输出。 分频器耦合到第二多路复用器以接收第二选择的输出以提供时钟信号。