公开(公告)号：US20180102797A1

公开(公告)日：2018-04-12

申请号：US15837791

申请日：2017-12-11

Applicant: Xilinx, Inc.

Inventor： Siok Wei Lim ,  Kok Lim Chan ,  Kee Hian Tan ,  Hongyuan Zhao ,  Chin Yang Koay ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04B1/04 ,  H03M9/00 ,  H02M3/158 ,  H03K17/687

CPC classification number: H04B1/04 ,  H02M3/158 ,  H03K17/163 ,  H03K17/6872 ,  H03K19/0175 ,  H03M9/00

Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

公开(公告)号：US09887710B1

公开(公告)日：2018-02-06

申请号：US15227853

申请日：2016-08-03

Applicant: Xilinx, Inc.

Inventor： Siok Wei Lim ,  Kok Lim Chan ,  Kee Hian Tan ,  Hongyuan Zhao ,  Chin Yang Koay ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04B1/04 ,  H03K17/687 ,  H03M9/00 ,  H02M3/158

CPC classification number: H04B1/04 ,  H02M3/158 ,  H03K17/163 ,  H03K17/6872 ,  H03K19/0175 ,  H03M9/00

Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

公开(公告)号：US09853642B1

公开(公告)日：2017-12-26

申请号：US15234667

申请日：2016-08-11

Applicant: Xilinx, Inc.

Inventor： Kee Hian Tan ,  Kok Lim Chan ,  Siok Wei Lim

IPC: H03K3/00 ,  H03K19/0185 ,  H03H17/06 ,  H03M9/00 ,  H04L25/03

CPC classification number: H03K19/018521 ,  H03H17/06 ,  H03M9/00 ,  H04L25/03343

Abstract: An example output driver includes a plurality of output circuits coupled in parallel between a first voltage supply node and a second voltage supply node. Each of the plurality of output circuits includes a differential input that is coupled to receive a logic signal of a plurality of logic signals and a differential output that is coupled to a common output node. The output driver further includes voltage regulator(s), coupled to the voltage supply node(s), and a current compensation circuit. The current compensation circuit includes a switch coupled in series with a current source, where the switch and the current source are coupled between the first voltage supply node and the second voltage supply node. An event detector is coupled to the switch to supply an enable signal and to control state of the enable signal based on presence of a pattern in the plurality of logic signals.

公开(公告)号：US20180041232A1

公开(公告)日：2018-02-08

申请号：US15227853

申请日：2016-08-03

Applicant: Xilinx, Inc.

Inventor： Siok Wei Lim ,  Kok Lim Chan ,  Kee Hian Tan ,  Hongyuan Zhao ,  Chin Yang Koay ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04B1/04 ,  H03M9/00 ,  H02M3/158 ,  H03K17/687

CPC classification number: H04B1/04 ,  H02M3/158 ,  H03K17/163 ,  H03K17/6872 ,  H03K19/0175 ,  H03M9/00

Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.

公开(公告)号：US10033412B2

公开(公告)日：2018-07-24

申请号：US15837791

申请日：2017-12-11

Applicant: Xilinx, Inc.

Inventor： Siok Wei Lim ,  Kok Lim Chan ,  Kee Hian Tan ,  Hongyuan Zhao ,  Chin Yang Koay ,  Yohan Frans ,  Kun-Yung Chang

IPC: H03K17/687 ,  H04B1/04 ,  H03M9/00 ,  H02M3/158

Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.