公开(公告)号：US20220059679A1

公开(公告)日：2022-02-24

申请号：US16996665

申请日：2020-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao LIU ,  Huicheng CHANG ,  Chien-Tai CHAN ,  Liang-Yin CHEN ,  Yee-Chia YEO ,  Szu-Ying CHEN

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.

公开(公告)号：US20210305092A1

公开(公告)日：2021-09-30

申请号：US16997616

申请日：2020-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Cheng CHEN ,  Huicheng CHANG ,  Fu-Ming HUANG ,  Kei-Wei CHEN ,  Liang-Yin CHEN ,  Tang-Kuei CHANG ,  Yee-Chia YEO ,  Wei-Wei LIANG ,  Ji CUI

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/532 ,  H01L23/522 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L23/535

Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

公开(公告)号：US20190287802A1

公开(公告)日：2019-09-19

申请号：US15920745

申请日：2018-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Shun CHANG ,  Chun-Feng NIEH ,  Huicheng CHANG

IPC: H01L21/033 ,  H01L21/3215 ,  H01L21/311 ,  H01L21/768

Abstract: Embodiments described herein relate generally to methods for forming a mask for patterning a feature in semiconductor processing. In an embodiment, a dielectric layer is formed over a substrate. A mask is formed over the dielectric layer. Forming the mask includes depositing a first layer over the dielectric layer; implanting in a first implant process a dopant species through a patterned material and into the first layer at a first energy; after implanting in the first implant process, implanting in a second implant process the dopant species through the patterned material and into the first layer at a second energy greater than the first energy; and forming mask portions of the mask comprising selectively removing portions of the first layer that are not implanted with the dopant species.

公开(公告)号：US20190131399A1

公开(公告)日：2019-05-02

申请号：US15797703

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao LIU ,  Huicheng CHANG ,  Chia-Cheng CHEN ,  Liang-Yin CHEN ,  Kuo-Ju CHEN ,  Chun-Hung WU ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC: H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/265 ,  H01L21/285 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20190006363A1

公开(公告)日：2019-01-03

申请号：US16105925

申请日：2018-08-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chang LIN ,  Chun-Feng NIEH ,  Huicheng CHANG ,  Hou-Yu CHEN ,  Yong-Yan LU

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/49 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7855

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

公开(公告)号：US20230369335A1

公开(公告)日：2023-11-16

申请号：US18358312

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Sathaiya Mahaveer DHANYAKUMAR ,  Huicheng CHANG ,  Keng-Chu LIN

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821

Abstract: The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair of source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.

公开(公告)号：US20210096473A1

公开(公告)日：2021-04-01

申请号：US16587710

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Huicheng CHANG ,  Chia-Cheng CHEN ,  Jyu-Horng SHIEH ,  Liang-Yin CHEN ,  Shu-Huei SUEN ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yi-Nien SU ,  Yung-Sung YEN ,  Chia-Fong CHANG ,  Ya-Wen YEH ,  Yu-Tien SHEN

IPC: G03F7/20 ,  H01L21/027

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

公开(公告)号：US20200343242A1

公开(公告)日：2020-10-29

申请号：US16924541

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Chia-Ling CHAN ,  Liang-Yin CHEN ,  Huicheng CHANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A method for forming a semiconductor structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes depositing a dopant source layer over the gate structure. The method also includes driving dopants of the dopant source layer into the fin structure. The method also includes removing the dopant source layer. The method also includes annealing the dopants in the fin structure to form a doped region. The method also includes etching the doped region and the fin structure below the doped region to form a recess. The method also includes growing a source/drain feature in the recess.

公开(公告)号：US20190157148A1

公开(公告)日：2019-05-23

申请号：US16021216

申请日：2018-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Po HSIEH ,  Su-Hao LIU ,  Hong-Chih LIU ,  Jing-Huei HUANG ,  Jie-Huang HUANG ,  Lun-Kuang TAN ,  Huicheng CHANG ,  Liang-Yin CHEN ,  Kuo-Ju CHEN

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a first contact plug and a first via plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The first contact plug is positioned over the source/drain structure. The first via plug is positioned over the first contact plug. The first via plug includes a first group IV element.

公开(公告)号：US20190103277A1

公开(公告)日：2019-04-04

申请号：US15952714

申请日：2018-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa LUAN ,  Huicheng CHANG ,  Cheng-Po CHAU ,  Wen-Yu KU ,  Yi-Fan CHEN ,  Chun-Yen PENG

IPC: H01L21/28 ,  H01L21/225 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.