公开(公告)号：US20230062940A1

公开(公告)日：2023-03-02

申请号：US17461329

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Sathaiya Mahaveer Dhanyakumar ,  Huicheng Chang ,  Keng-Chu Lin

IPC: H01L27/092 ,  H01L21/8238

Abstract: The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair or source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.

公开(公告)号：US20220285515A1

公开(公告)日：2022-09-08

申请号：US17550759

申请日：2021-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Wei-Yen Woon

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/786 ,  H01L29/66

Abstract: The present disclosure provides source/drain epitaxial structures and source/drain contacts wrapped with graphene layers in fin structures of FETs, and fabricating methods thereof. In some embodiments, a disclosed semiconductor device includes a fin structure on a substrate. The fin structure includes an epitaxial region. The semiconductor device further includes a metal contact above the epitaxial region, and a graphene film covering a top surface and sidewalls of the epitaxial region and covering a bottom surface and sidewalls of the metal contact.

公开(公告)号：US20210193511A1

公开(公告)日：2021-06-24

申请号：US16721762

申请日：2019-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li WANG ,  Shuen-Shin LIANG ,  Yu-Yun PENG ,  Fang-Wei LEE ,  Chia-Hung CHU ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/306

Abstract: A multi-layer interconnect structure with a self-aligning barrier structure and a method for fabricating the same is disclosed. For example, the method includes forming a via through an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and a contact structure, pre-cleaning the via with a metal halide, forming a barrier structure on the contact structure in-situ during the pre-cleaning of the via with the metal halide, and depositing a second metal in the via on top of the barrier structure.

公开(公告)号：US20230010280A1

公开(公告)日：2023-01-12

申请号：US17738956

申请日：2022-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Wei-Yen WOON

IPC: H01L23/528 ,  H01L27/088 ,  H01L23/522 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/16

Abstract: An integrated circuit (IC) with a semiconductor device and an interconnect structure with carbon layers and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a source/drain region on the fin structure, forming a contact structure on the S/D region, forming an oxide layer on the contact structure, forming a conductive carbon line within a first insulating carbon layer on the oxide layer, forming a second insulating carbon layer on the first insulating carbon layer, and forming a via within the second insulating carbon layer.

公开(公告)号：US20220157936A1

公开(公告)日：2022-05-19

申请号：US17097959

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Dhanyakumar Mahaveer SATHAIYA ,  Huicheng CHANG ,  Ko-Feng CHEN ,  Keng-Chu LIN

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

Abstract: The present disclosure is directed to a method for the fabrication of isolation structures between source/drain (S/D)) epitaxial structures of stacked transistor structures. The method includes depositing an oxygen-free dielectric material in an opening over a first epitaxial structure, where the oxygen-free dielectric material covers top surfaces of the first epitaxial structure and sidewall surfaces of the opening. The method also includes exposing the oxygen-free dielectric material to an oxidizing process to oxidize the oxygen-free dielectric material so that the oxidizing process does not oxidize a portion of the oxygen-free dielectric material on the first epitaxial structure. Further, etching the oxidized oxygen-free dielectric material and forming a second epitaxial layer on the oxygen-free dielectric material not removed by the etching to substantially the opening.

公开(公告)号：US20240243009A1

公开(公告)日：2024-07-18

申请号：US18618815

申请日：2024-03-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li WANG ,  Shuen-Shin LIANG ,  Yu-Yun PENG ,  Fang-Wei LEE ,  Chia-Hung CHU ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/30604 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

Abstract: A device includes source/drain regions, a gate structure, a source/drain contact, and a tungsten structure. The source/drain regions are over a substrate. The gate structure is between the source/drain regions. The source/drain contact is over one of the source/drain regions. The tungsten structure is over the source/drain contact. The tungsten structure includes a lower portion and an upper portion above the lower portion. The upper portion has opposite sidewalls respectively set back from opposite sidewalls of the lower portion of the tungsten structure.

公开(公告)号：US20230015572A1

公开(公告)日：2023-01-19

申请号：US17377519

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN ,  Yu-Yun PENG

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/45 ,  H01L29/66 ,  H01L29/40

Abstract: The present disclosure describes a semiconductor device that includes a transistor. The transistor includes a source/drain region that includes a front surface and a back surface opposite to the front surface. The transistor includes a salicide region on the back surface and a channel region in contact with the source/drain region. The channel region has a front surface co-planar with the front surface of the source/drain region. The transistor further includes a gate structure disposed on a front surface of the channel region. The semiconductor device also includes a backside contact structure that includes a conductive contact in contact with the salicide region and a liner layer surrounding the conductive contact.

公开(公告)号：US20230369335A1

公开(公告)日：2023-11-16

申请号：US18358312

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Sathaiya Mahaveer DHANYAKUMAR ,  Huicheng CHANG ,  Keng-Chu LIN

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821

Abstract: The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair of source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.

公开(公告)号：US20210226057A1

公开(公告)日：2021-07-22

申请号：US16744480

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung CHU ,  Sung-Li WANG ,  Fang-Wei LEE ,  Jung-Hao CHANG ,  Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/311 ,  H01L29/417

Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes growing a source/drain epitaxial structure over the fin structure. The method also includes depositing a first dielectric layer surrounding the source/drain epitaxial structure. The method also includes forming a contact structure in the first dielectric layer over the source/drain epitaxial structure. The method also includes depositing a second dielectric layer over the first dielectric layer. The method also includes forming a hole in the second dielectric layer to expose the contact structure. The method also includes etching the contact structure to enlarge the hole in the contact structure. The method also includes filling the hole with a conductive material.

公开(公告)号：US20230387254A1

公开(公告)日：2023-11-30

申请号：US18446674

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith KHADERBAD ,  Keng-Chu LIN ,  Yu-Yun PENG

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/66553 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4991 ,  H01L29/78618 ,  H01L29/66742 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/66545 ,  H01L21/02603 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/31111 ,  H01L27/0886 ,  H01L21/823481 ,  H01L21/0234

Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.