公开(公告)号：US20230386834A1

公开(公告)日：2023-11-30

申请号：US18447869

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Kai YANG ,  Yu-Tien SHEN ,  Hsiang-Ming CHANG ,  Chun-Yen CHANG ,  Ya-Hui CHANG ,  Wei-Ting CHIEN ,  Chia-Cheng CHEN ,  Liang-Yin CHEN

IPC: H01L21/027 ,  H01L21/311 ,  G03F7/00 ,  H01L21/3115 ,  H01L21/768

CPC classification number: H01L21/0273 ,  H01L21/31144 ,  G03F7/70058 ,  H01L21/31155 ,  H01L21/76877

Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.

公开(公告)号：US20190165099A1

公开(公告)日：2019-05-30

申请号：US15825533

申请日：2017-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Liang-Yin CHEN

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L21/02 ,  H01L21/223 ,  H01L21/324 ,  H01L29/66

Abstract: Embodiments disclosed herein relate generally to forming a source/drain region with a high surface dopant concentration at an upper surface of the source/drain region, to which a conductive feature may be formed. In an embodiment, a structure includes an active area on a substrate, a dielectric layer over the active area, and a conductive feature through the dielectric layer to the active area. The active area includes a source/drain region. The source/drain region includes a surface dopant region at an upper surface of the source/drain region, and includes a remainder portion of the source/drain region having a source/drain dopant concentration. The surface dopant region includes a peak dopant concentration proximate the upper surface of the source/drain region. The peak dopant concentration is at least an order of magnitude greater than the source/drain dopant concentration. The conductive feature contacts the source/drain region at the upper surface of the source/drain region.

公开(公告)号：US20190027473A1

公开(公告)日：2019-01-24

申请号：US15652719

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Chia-Ling CHAN ,  Liang-Yin CHEN ,  Huicheng CHANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a gate structure and a source/drain feature. The gate structure is positioned over a fin structure. The source/drain feature is positioned adjacent to the gate structure. A portion of the source/drain feature embedded in the fin structure has an upper sidewall portion adjacent to a top surface of the fin structure and a lower sidewall portion below the upper sidewall portion. A first curve radius of the upper sidewall portion is different from a second curve radius of the lower sidewall portion in a cross-sectional view substantially along the longitudinal direction of the fin structure.

公开(公告)号：US20150076575A1

公开(公告)日：2015-03-19

申请号：US14031057

申请日：2013-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei WU ,  Wei-Shuo KAO ,  Chia-Cheng CHEN ,  Kuang Ting CHEN

IPC: H01L27/11 ,  H01L29/94

CPC classification number: H01L27/1116 ,  G11C7/12 ,  G11C7/18 ,  G11C11/412 ,  G11C11/419 ,  G11C2207/005 ,  H01L29/94

Abstract: An integrated circuit includes a plurality of metal layers of bit cells of a memory cell array disposed in a first metal layer and extending in a first direction, a plurality of word lines of the memory cell array disposed in a second metal layer and extending in a second direction that is different from the first direction, and at least two conductive traces disposed in a third metal layer substantially adjacent to each other and extending at least partially across the memory cell array, a first one of the at least two conductive traces coupled to a driving source node of a write assist circuit, and a second conductive trace of the at least two conductive traces coupled to an enable input of the write-assist circuit, where the at least two conductive traces form at least one embedded capacitor having a capacitive coupling to the bit line.

Abstract translation: 一种集成电路包括设置在第一金属层中并沿第一方向延伸的存储单元阵列的位单元的多个金属层，所述存储单元阵列的多个字线设置在第二金属层中并在 与第一方向不同的第二方向，以及布置在基本上彼此相邻并且至少部分地跨过存储单元阵列延伸的第三金属层中的至少两个导电迹线，所述至少两个导电迹线中的第一导电迹线耦合到 写辅助电路的驱动源节点和耦合到写辅助电路的使能输入的至少两个导电迹线的第二导电迹线，其中所述至少两个导电迹线形成至少一个嵌入式电容器，其具有电容 耦合到位线。

公开(公告)号：US20250113551A1

公开(公告)日：2025-04-03

申请号：US18404785

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Sih-Jie LIU ,  Liang-Yin CHEN ,  Chi On CHUI

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A method includes: forming a stack of nanostructures over a substrate; forming a source/drain opening adjacent the stack of nanostructures; forming a semiconductor layer in the source/drain opening; forming an amorphous semiconductor layer by performing an ion implantation on the semiconductor layer; and forming a recrystallized source/drain by annealing the amorphous semiconductor layer.

公开(公告)号：US20210096473A1

公开(公告)日：2021-04-01

申请号：US16587710

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Huicheng CHANG ,  Chia-Cheng CHEN ,  Jyu-Horng SHIEH ,  Liang-Yin CHEN ,  Shu-Huei SUEN ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yi-Nien SU ,  Yung-Sung YEN ,  Chia-Fong CHANG ,  Ya-Wen YEH ,  Yu-Tien SHEN

IPC: G03F7/20 ,  H01L21/027

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

公开(公告)号：US20200343242A1

公开(公告)日：2020-10-29

申请号：US16924541

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Chia-Ling CHAN ,  Liang-Yin CHEN ,  Huicheng CHANG

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A method for forming a semiconductor structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes depositing a dopant source layer over the gate structure. The method also includes driving dopants of the dopant source layer into the fin structure. The method also includes removing the dopant source layer. The method also includes annealing the dopants in the fin structure to form a doped region. The method also includes etching the doped region and the fin structure below the doped region to form a recess. The method also includes growing a source/drain feature in the recess.

公开(公告)号：US20220102139A1

公开(公告)日：2022-03-31

申请号：US17353400

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Kai YANG ,  Yu-Tien SHEN ,  Hsiang-Ming CHANG ,  Chun-Yen CHANG ,  Ya-Hui CHANG ,  Wei-Ting CHIEN ,  Chia-Cheng CHEN ,  Liang-Yin CHEN

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3115 ,  G03F7/20

Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.

公开(公告)号：US20210305092A1

公开(公告)日：2021-09-30

申请号：US16997616

申请日：2020-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Cheng CHEN ,  Huicheng CHANG ,  Fu-Ming HUANG ,  Kei-Wei CHEN ,  Liang-Yin CHEN ,  Tang-Kuei CHANG ,  Yee-Chia YEO ,  Wei-Wei LIANG ,  Ji CUI

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/532 ,  H01L23/522 ,  H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L23/535

Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

公开(公告)号：US20190157456A1

公开(公告)日：2019-05-23

申请号：US16038866

申请日：2018-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng CHEN ,  Su-Hao LIU ,  Kuo-Ju CHEN ,  Liang-Yin CHEN

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L27/088

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes forming a modified region in the epitaxial structure. The modified region has lower crystallinity than an inner portion of the epitaxial structure and extends along an entirety of an exposed surface of the epitaxial structure. The method also includes forming a semiconductor-metal compound region on the epitaxial structure. All or some of the modified region is transformed into the semiconductor-metal compound region.