公开(公告)号：US20190103277A1

公开(公告)日：2019-04-04

申请号：US15952714

申请日：2018-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hongfa LUAN ,  Huicheng CHANG ,  Cheng-Po CHAU ,  Wen-Yu KU ,  Yi-Fan CHEN ,  Chun-Yen PENG

IPC: H01L21/28 ,  H01L21/225 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

公开(公告)号：US20170207117A1

公开(公告)日：2017-07-20

申请号：US15473166

申请日：2017-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun WANG ,  De-Wei YU ,  Ziwei FANG ,  Yi-Fan CHEN

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/522 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3115 ,  H01L29/417

CPC classification number: H01L21/76825 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The FIT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.

公开(公告)号：US20190229012A1

公开(公告)日：2019-07-25

申请号：US16371847

申请日：2019-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun WANG ,  De-Wei YU ,  Ziwei FANG ,  Yi-Fan CHEN

IPC: H01L21/768 ,  H01L21/265 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/324 ,  H01L23/48

CPC classification number: H01L21/76825 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.