公开(公告)号：US20170005095A1

公开(公告)日：2017-01-05

申请号：US15267328

申请日：2016-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Cing-Yao Chan ,  Chun-Ying Wang ,  Jen-Pan Wang

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/10 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L27/0928 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/823807 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/7842

Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.

Abstract translation: 本公开涉及具有沟道区的晶体管器件，该晶体管器件包括具有提高器件性能的多个不同层的夹层膜堆叠以及相关联的器件。 在一些实施例中，晶体管器件具有设置在半导体衬底内的源极区域和漏极区域。 夹层薄膜叠层横向放置在源区和漏区之间。 夹层膜堆叠具有下层，设置在下层上的碳掺杂半导体材料的中间层和设置在中间层上的上层。 栅极结构设置在夹层膜堆叠之上。 栅极结构被配置为控制位于源极区域和漏极区域之间的沟道区域中的电荷载流子的流动。

公开(公告)号：US20150129976A1

公开(公告)日：2015-05-14

申请号：US14079950

申请日：2013-11-14

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Chih-Fu Chang ,  Jen-Pan Wang

IPC: H01L29/45 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/3205 ,  H01L21/321

CPC classification number: H01L21/02532 ,  H01L21/0262 ,  H01L21/28518 ,  H01L21/32051 ,  H01L21/32053 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76843 ,  H01L21/76855

Abstract: A semiconductor device includes a substrate, an epi-layer, an etch stop layer, an interlayer dielectric (ILD) layer, a silicide layer cap and a contact plug. The substrate has a first portion and a second portion neighboring to the first portion. The etch stop layer is disposed on the second portion. The ILD layer is disposed on the etch stop layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the ILD layer.

Abstract translation: 半导体器件包括衬底，外延层，蚀刻停止层，层间电介质（ILD）层，硅化物层帽和接触插塞。 衬底具有与第一部分相邻的第一部分和第二部分。 蚀刻停止层设置在第二部分上。 ILD层设置在蚀刻停止层上。 硅化物盖设置在外延层上。 接触插塞设置在硅化物盖上并被ILD层包围。

公开(公告)号：US10608094B2

公开(公告)日：2020-03-31

申请号：US15877395

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Tsun Tsai ,  I-Chih Chen ,  Chih-Mu Huang ,  Jiun-Jie Huang ,  Jen-Pan Wang

IPC: H01L29/423 ,  H01L29/40 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are disclosed. A semiconductor device includes a substrate, a gate structure over the substrate, a spacer and a source/drain region. The gate structure is disposed over the substrate. The spacer is disposed on a sidewall of the gate structure, wherein the spacer has a top surface lower than a top surface of the gate structure. The source/drain region is disposed adjacent to a sidewall of the spacer.

公开(公告)号：US20150263092A1

公开(公告)日：2015-09-17

申请号：US14205911

申请日：2014-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ling-Sung Wang ,  Chih-Mu Huang ,  Cing-Yao Chan ,  Chun-Ying Wang ,  Jen-Pan Wang

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/306 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L27/0928 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/823807 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/7842

Abstract: The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the method is performed by selectively etching a semiconductor substrate to form a recess along a top surface of the semiconductor substrate. A sandwich film stack having a plurality of nested layers is formed within the recess. At least two of the nested layers include different materials that improve different aspects of the performance of the transistor device. A gate structure is formed over the sandwich film stack. The gate structure controls the flow of charge carriers in a channel region having the sandwich film stack, which is laterally positioned between a source region and a drain region disposed within the semiconductor substrate.

Abstract translation: 本公开涉及一种形成晶体管器件的方法，该晶体管器件具有沟道区域，该沟道区域包括具有提高器件性能的多个不同层的夹层膜堆叠以及相关联的器件。 在一些实施例中，通过选择性地蚀刻半导体衬底以沿着半导体衬底的顶表面形成凹槽来执行该方法。 在凹部内形成具有多个嵌套层的夹层膜叠层。 至少两个嵌套层包括改善晶体管器件性能的不同方面的不同材料。 在三明治薄膜叠层上形成栅极结构。 栅极结构控制具有夹层膜堆叠的沟道区域中的载流子的流动，其横向地位于设置在半导体衬底内的源极区域和漏极区域之间。

公开(公告)号：US09110386B2

公开(公告)日：2015-08-18

申请号：US14300499

申请日：2014-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Pan Wang ,  Chien-Hsuan Liu ,  Ching-Hsien Chen ,  Chao-Chi Chen

IPC: G03F7/20 ,  G03F9/00

CPC classification number: G03F7/70641 ,  G03F7/70341 ,  G03F9/7026 ,  G03F9/7034 ,  G03F9/7053

Abstract: A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process.

Abstract translation: 一种方法包括提供在衬底上具有至少一层材料的半导体衬底。 对基板施加声音，使得声波被材料层的顶表面反射。使用传感器检测声波。 基于检测到的声波来确定顶面的形貌。 确定的地形用于控制浸没光刻工艺。