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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    14.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20160336320A1

    公开(公告)日：2016-11-17

    申请号：US14714231

    申请日：2015-05-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chih-Han LIN

    IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/49

    CPC classification number: H01L27/0924 ,  H01L21/32137 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545

    Abstract: A semiconductor device includes first and second Fin FETs and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending in a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending in the second direction. When viewed from above, an end shape the separation plug has a concave curved shape, while an end of the first gate electrode abutting the separation plug has a convex curved shape.

    Abstract translation: 半导体器件包括第一和第二Fin FET以及由绝缘材料制成并分布在第一和第二Fin FET之间的分离插头。 第一Fin FET包括沿第一方向延伸的第一鳍结构，形成在第一鳍结构上的第一栅极电介质和形成在第一栅极电介质上并沿垂直于第一方向的第二方向延伸的第一栅电极。 第二Fin FET包括第二鳍结构，形成在第二鳍结构上的第二栅极电介质和形成在第一栅极电介质上并沿第二方向延伸的第二栅电极。 当从上方观察时，分离塞具有凹形弯曲形状的端部形状，而与分离塞抵接的第一栅电极的端部具有凸曲面形状。

    FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME
    16.
    发明申请
    FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME 有权
    FIN场效应晶体管（FINFET）器件及其形成方法

    公开(公告)号：US20150236132A1

    公开(公告)日：2015-08-20

    申请号：US14181320

    申请日：2014-02-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Che-Cheng CHANG ,  Chang-Yin CHEN ,  Jr-Jung LIN ,  Chih-Han LIN ,  Yung-Jung CHANG

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7848 ,  H01L29/785

    Abstract: Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a fin structure extending above a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure also includes a gate electrode formed on the gate dielectric layer. The FinFET device structure further includes a number of gate spacers formed on sidewalls of the gate electrode. The gate spacers are in direct contact with the fin structure.

    Abstract translation: 提供了用于形成鳍状场效应晶体管（FinFET）器件结构的实施例。 FinFET器件结构包括在衬底上延伸的翅片结构和形成在鳍结构上的栅极电介质层。 FinFET器件结构还包括形成在栅极介电层上的栅电极。 FinFET器件结构还包括形成在栅电极的侧壁上的多个栅极间隔物。 栅极间隔件与翅片结构直接接触。

    INTERCONNECTION STRUCTURE WITH ANTI-ADHESION LAYER
    17.
    发明申请
    INTERCONNECTION STRUCTURE WITH ANTI-ADHESION LAYER 有权

    公开(公告)号：US20210233806A1

    公开(公告)日：2021-07-29

    申请号：US17230701

    申请日：2021-04-14

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Che-Cheng CHANG ,  Chih-Han LIN

    IPC: H01L21/768 ,  H01L23/528

    Abstract: A device comprises a first metal structure, a dielectric structure, a dielectric residue, and a second metal structure. The dielectric structure is over the first metal structure. The dielectric structure has a stepped sidewall structure. The stepped sidewall structure comprises a lower sidewall and an upper sidewall laterally set back from the lower sidewall. The dielectric residue is embedded in a recessed region in the lower sidewall of the stepped sidewall structure of the dielectric structure. The second metal structure extends through the dielectric structure to the first metal structure.

    SEMICONDUCTOR DEVICE
    18.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210111266A1

    公开(公告)日：2021-04-15

    申请号：US17129253

    申请日：2020-12-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

    IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28

    Abstract: A device includes a semiconductive fin having source and drain regions and a channel region between the source and drain regions, a gate feature over the channel region of the semiconductive fin, a first spacer around the gate feature, source and drain features respectively in the source and drain regions of the semiconductive fin, an interlayer dielectric layer around the first spacer, and a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features.

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
    19.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210074840A1

    公开(公告)日：2021-03-11

    申请号：US16562406

    申请日：2019-09-05

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02

    Abstract: A semiconductor device includes an isolation insulating layer disposed over a substrate, a semiconductor fin disposed over the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin being embedded in the isolation insulating layer, a gate structure disposed over the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer, gate sidewall spacers disposed over opposing side faces of the gate structure, and a source/drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining part of the semiconductor fin. The first epitaxial growth enhancement layer is in contact with the source/drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

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