公开(公告)号：US09978613B1

公开(公告)日：2018-05-22

申请号：US15452026

申请日：2017-03-07

Applicant: Texas Instruments Incorporated

Inventor： You Chye How

IPC: H01L21/60 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01L21/78 ,  H01L25/00 ,  H01L25/16

CPC classification number: H01L21/561 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/6836 ,  H01L25/165 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014

Abstract: Disclosed examples include a method of making a semiconductor die package comprising arranging at least one preformed die attach pad and at least two preformed leads on a lead frame carrier in a predetermined configuration to form a lead frame, attaching a semiconductor die to the at least one preformed die attach pad, wire bonding the semiconductor die to the at least two preformed leads, forming a molding structure including at least part of the semiconductor die and the at least two preformed leads, and removing the molding structure from the lead frame carrier.

公开(公告)号：US20170053883A1

公开(公告)日：2017-02-23

申请号：US15254948

申请日：2016-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： You Chye How ,  Huay Yann Tay

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/4825 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49589 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02205 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/11618 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13078 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13616 ,  H01L2224/13647 ,  H01L2224/1601 ,  H01L2224/1607 ,  H01L2224/16113 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/92225 ,  H01L2924/01327 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An integrated circuit (“IC”) package including at least one IC die having a first side with at least two adjacent bump pads thereon and a second side opposite the first side; a first substrate having a first side with a plurality of electrical contact surfaces thereon; and a plurality of copper pillars, each having a first end attached to one of the adjacent bump pads and a second end attached to one of the electrical contact surfaces.

Abstract translation: 一种集成电路（“IC”）封装，包括至少一个IC裸片，其具有第一侧和至少两个相邻的凸块焊盘和与第一侧相对的第二侧; 第一基板，其上具有多个电接触表面的第一侧; 以及多个铜柱，每个铜柱具有附接到相邻凸块之一的第一端和连接到电接触表面之一的第二端。

公开(公告)号：US09202778B2

公开(公告)日：2015-12-01

申请号：US13974323

申请日：2013-08-23

Applicant: Texas Instruments Incorporated

Inventor： You Chye How ,  Maria Christina Bernando Violante

IPC: H01L23/52 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/6836 ,  H01L23/00 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/94 ,  H01L25/0655 ,  H01L2221/68377 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1515 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2924/0781

Abstract: An integrated circuit package having a die attach paddle, a power die mounted on the die attach paddle and a controller die mounted on the die attach paddle. The die attach paddle has at least one recessed portion at least partially underlying the controller die.

Abstract translation: 一种集成电路封装，其具有管芯附接焊盘，安装在管芯附着焊盘上的电源管芯和安装在管芯连接板上的控制器管芯。 管芯附接板具有至少部分至少部分地位于控制器管芯下方的凹陷部分。

公开(公告)号：US20240055313A1

公开(公告)日：2024-02-15

申请号：US18494198

申请日：2023-10-25

Applicant: Texas Instruments Incorporated

Inventor： Michael Todd Wyant ,  Matthew John Sherbin ,  Christopher Daniel Manack ,  Patrick Francis Thompson ,  You Chye How

IPC: H01L23/31 ,  H01L23/552 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/3185 ,  H01L23/3171 ,  H01L23/552 ,  H01L21/568 ,  H01L21/78 ,  H01L21/561 ,  H01L2221/68336 ,  H01L21/6836

Abstract: In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.

公开(公告)号：US10381293B2

公开(公告)日：2019-08-13

申请号：US15003238

申请日：2016-01-21

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@Eugene Lee ,  Chong Han Lim ,  You Chye How

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/495

Abstract: An integrated circuit (IC) package includes a first leadframe having a top surface and a bottom surface. An IC die has an active side coupled to the first leadframe bottom surface and has a back side. A second leadframe has a top surface and a bottom surface. The back side of said IC chip is coupled to the top surface of the second leadframe.

公开(公告)号：US09123626B1

公开(公告)日：2015-09-01

申请号：US14192402

申请日：2014-02-27

Applicant: Texas Instruments Incorporated

Inventor： You Chye How ,  Siew Kee Lee ,  Huay Yann Tay

IPC: H01L23/48 ,  H01L29/40 ,  H01L21/00 ,  H01L25/16 ,  H01L23/495 ,  H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L21/768 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/165 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49541 ,  H01L23/53214 ,  H01L23/53228 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06102 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/81801 ,  H01L2224/9212 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/19106 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00014

Abstract: A method for packaging integrated circuit die such that each package includes die with integrated passive components mounted to either the back surface, the active surface or both the back and active surfaces of the die.

Abstract translation: 一种用于封装集成电路管芯的方法，使得每个封装包括具有安装到管芯的背表面，活性表面或后表面和有源表面的集成无源元件的管芯。

公开(公告)号：US20150054145A1

公开(公告)日：2015-02-26

申请号：US13974323

申请日：2013-08-23

Applicant: Texas Instruments Incorporated

Inventor： You Chye How ,  Maria Christina Bernardo Violante

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/6836 ,  H01L23/00 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/94 ,  H01L25/0655 ,  H01L2221/68377 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1515 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2924/0781

Abstract: An integrated circuit package having a die attach paddle, a power die mounted on the die attach paddle and a controller die mounted on the die attach paddle. The die attach paddle has at least one recessed portion at least partially underlying the controller die.

Abstract translation: 一种集成电路封装，其具有管芯附接焊盘，安装在管芯附着焊盘上的电源管芯和安装在管芯连接板上的控制器管芯。 管芯附接板具有至少部分至少部分地位于控制器管芯下方的凹陷部分。

公开(公告)号：US20140346656A1

公开(公告)日：2014-11-27

申请号：US13902916

申请日：2013-05-27

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  You Chye How

IPC: H01L23/495

CPC classification number: H01L21/4828 ,  H01L21/4825 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L24/97 ,  H01L2924/181 ,  H01L2924/00

Abstract: A multilevel leadframe for an integrated circuit package is provided that has a plurality of lead lines formed in a first level and bond pads formed in a second level. A first set of bond pads is arranged in a first row and are separated from an adjacent bond pad by a bond pad clearance distance. A second set of bond pads is arranged in second row adjacent the first row of bond pads. Each bond pad in the second row may be connected to one of the plurality of lead lines on the first level that is routed between adjacent bond pads in the first row. Since the bond pads in the first row are on a different level then the lead lines, the bond pads may be spaced close together.

Abstract translation: 提供了一种用于集成电路封装的多级引线框架，其具有形成在第一级中的多条引线和形成在第二级中的接合焊盘。 第一组接合焊盘被布置在第一行中并且通过接合焊盘间隙距离与相邻接合焊盘分开。 第二组接合焊盘被布置在与第一排接合焊盘相邻的第二行中。 第二行中的每个接合焊盘可以连接到在第一级中的相邻接合焊盘之间路由的第一级上的多条引线之一。 由于第一行中的接合焊盘处于不同的电平，所以引线，接合焊盘可以彼此靠近地间隔开。

公开(公告)号：US11830791B2

公开(公告)日：2023-11-28

申请号：US16514436

申请日：2019-07-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： You Chye How ,  Anis Fauzi Bin Abdul Aziz

IPC: H01L23/495 ,  H01L21/50 ,  H02H5/04 ,  H01L21/60

CPC classification number: H01L23/49513 ,  H01L21/50 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49582 ,  H02H5/042 ,  H02H5/047 ,  H01L2021/60015

Abstract: A semiconductor package includes a die pad and leads extending from the die pad. Each lead has a free end with outer surfaces extending at angles from one another. An electrically conductive plating material covers at least portions of the outer surfaces. A die attached to the die pad is electrically connected to the leads. An insulating layer extends over the leads and the die such that the free ends of the leads are exposed.

公开(公告)号：US10079162B1

公开(公告)日：2018-09-18

申请号：US15955435

申请日：2018-04-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： You Chye How

IPC: H01L21/60 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/78 ,  H01L25/16 ,  H01L23/495 ,  H01L23/498

Abstract: Disclosed examples include a method of making a semiconductor die package comprising arranging at least one preformed die attach pad and at least two preformed leads on a lead frame carrier in a predetermined configuration to form a lead frame, attaching a semiconductor die to the at least one preformed die attach pad, wire bonding the semiconductor die to the at least two preformed leads, forming a molding structure including at least part of the semiconductor die and the at least two preformed leads, and removing the molding structure from the lead frame carrier.