公开(公告)号：US09859197B2

公开(公告)日：2018-01-02

申请号：US14691660

申请日：2015-04-21

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Sueann Lim Wei Fen ,  Sarel Bin Ismail

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/00 ,  H01L23/532 ,  H01L23/544 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49541 ,  H01L21/4821 ,  H01L21/4842 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/5328 ,  H01L23/544 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/27312 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/83862 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A method of making an integrated circuit (“IC”) device includes forming a lead frame in a lead frame strip. Only portions of the lead frame are plated with a conductor. A die pad is attached to an unplated portion of said lead frame.

公开(公告)号：US09496206B2

公开(公告)日：2016-11-15

申请号：US14683277

申请日：2015-04-10

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi Bin Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L21/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/49551 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49586 ,  H01L23/49589 ,  H01L51/56 ,  H01L2224/97

Abstract: A leadframe (100) for electronic systems comprising a first sub-leadframe (110) connected by links (150) to a second sub-leadframe (120), the first and second sub-leadframe connected by tiebars (111, 121) to a frame (130); and each link having a neck (151) suitable for bending the link, the necks arrayed in a line (170) operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.

Abstract translation: 一种用于电子系统的引线框架（100），包括通过链接（150）连接到第二子引线框架（120）的第一子引线框架（110），所述第一和第二子引线框架通过连杆（111,121）连接到 框架（130）; 并且每个连杆具有适于弯曲所述连杆的颈部（151），所述颈部排列成可操作为用于使所述颈部可操作为旋转枢轴的所述第二子引线框架朝向所述第一子引线框架弯曲的轴线的线（170）。

公开(公告)号：US11348806B2

公开(公告)日：2022-05-31

申请号：US14581233

申请日：2014-12-23

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Shu Hui Ooi ,  Anis Fauzi Abdul Aziz ,  Wei Fen Sueann Lim

IPC: H01L21/44 ,  H01L21/48 ,  C25D7/00 ,  C25D17/08 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  C25D5/02 ,  H01L23/31

Abstract: A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral faces thereof. The method includes providing a plurality of Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces exposed on bottom faces thereof. The method further includes batch electroplating the severed unplated lead surfaces of the plurality of Flat No-Lead Packages.

公开(公告)号：US20200091111A1

公开(公告)日：2020-03-19

申请号：US16688905

申请日：2019-11-19

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Khoo Yien Sien

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L21/78

Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.

公开(公告)号：US09842807B2

公开(公告)日：2017-12-12

申请号：US14887047

申请日：2015-10-19

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Wei Fen Sueann Lim

IPC: H01L23/538 ,  H01L23/495 ,  H01L21/768 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/0579 ,  H01L2224/05839 ,  H01L2224/08245 ,  H01L2224/29009 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73251 ,  H01L2224/73265 ,  H01L2224/9222 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/35121 ,  H01L2924/3862 ,  H01L2924/00014 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00 ,  H01L2924/0781 ,  H01L2924/0665 ,  H01L2224/08 ,  H01L2224/80 ,  H01L2224/48

Abstract: An integrated circuit (IC) die including a top surface and a bottom surface, a plurality of spaced apart ground connection traces positioned between the top surface and the bottom surface; with a hole in the die exposing the plurality of spaced apart ground connection traces.

公开(公告)号：US20160204052A1

公开(公告)日：2016-07-14

申请号：US14592011

申请日：2015-01-08

Applicant: Texas Instruments Incorporated

Inventor： Sueann Lim Wei Fen ,  Lee Han Meng@ Eugene Lee ,  Anis Fauzi Bin Abdul Aziz

IPC: H01L23/495 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49052 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8346 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01028 ,  H01L2924/01027 ,  H01L2224/85 ,  H01L2224/83

Abstract: A semiconductor device has a leadframe with a first (401a) and a parallel second surface, and an assembly pad (410) bordered by two opposing sides, which include a plurality of through-holes (420) from the first to the second pad surface. Another pad side includes one or more elongated windows (421) between the pad surfaces. The second pad surface includes a plurality of grooves. The leadframe further has a plurality of leads (430) with opposite elongated sides castellated by indents (431). Layers (440) of bondable metals are restricted to localized areas surrounding bond spots. A semiconductor chip (450) is attached to the pad and wire-bonded (460) to the bond spots. A package (470) encapsulates the chip, wires, pad, and lead portions, and secures the leadframe into the package by filling the through-holes, windows, grooves, and indents.

Abstract translation: 半导体器件具有带有第一（401a）和平行的第二表面的引线框和由两个相对的边界定的组装焊盘（410），其包括从第一焊盘表面到第二焊盘表面的多个通孔（420） 。 另一衬垫侧包括在垫表面之间的一个或多个细长窗（421）。 第二垫表面包括多个槽。 引线框还具有多个引线（430），其具有由凹口（431）铸造的相对的细长边。 可焊接金属层（440）限于粘结点附近的局部区域。 将半导体芯片（450）附接到焊盘并且引线键合（460）到接合点。 封装（470）封装芯片，电线，焊盘和引线部分，并且通过填充通孔，窗口，凹槽和凹口来将引线框固定到封装中。

公开(公告)号：US11742263B2

公开(公告)日：2023-08-29

申请号：US16953189

申请日：2020-11-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi Bin Abdul Aziz ,  Wei Fen Sueann Lim

IPC: H01L23/495 ,  H01L21/78 ,  H10K71/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49551 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49555 ,  H01L23/49568 ,  H10K71/00 ,  H01L23/49586 ,  H01L23/49589 ,  H01L2224/97

Abstract: A leadframe for electronic systems comprising a first sub-leadframe connected by links to a second sub-leadframe, the first and second sub-leadframe connected by tiebars to a frame; and each link having a neck suitable for bending the link, the necks arrayed in a line operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.

公开(公告)号：US10720406B2

公开(公告)日：2020-07-21

申请号：US16688905

申请日：2019-11-19

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Khoo Yien Sien

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/498 ,  H01L23/495 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.

公开(公告)号：US20160300784A1

公开(公告)日：2016-10-13

申请号：US14683277

申请日：2015-04-10

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi Bin Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49551 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49586 ,  H01L23/49589 ,  H01L51/56 ,  H01L2224/97

Abstract: A leadframe (100) for electronic systems comprising a first sub-leadframe (110) connected by links (150) to a second sub-leadframe (120), the first and second sub-leadframe connected by tiebars (111, 121) to a frame (130); and each link having a neck (151) suitable for bending the link, the necks arrayed in a line (170) operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.

Abstract translation: 一种用于电子系统的引线框架（100），包括通过链接（150）连接到第二子引线框架（120）的第一子引线框架（110），所述第一和第二子引线框架通过连杆（111,121）连接到 框架（130）; 并且每个连杆具有适于弯曲所述连杆的颈部（151），所述颈部排列成可操作为用于使所述颈部可操作为旋转枢轴的所述第二子引线框架朝向所述第一子引线框架弯曲的轴线的线（170）。

公开(公告)号：US20160240390A1

公开(公告)日：2016-08-18

申请号：US15138298

申请日：2016-04-26

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  You Chye How

IPC: H01L21/48

CPC classification number: H01L21/4828 ,  H01L21/4825 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L24/97 ,  H01L2924/181 ,  H01L2924/00

Abstract: A method for forming a multilevel leadframe for an integrated circuit is provided. A conductive sheet is etched from one side to form a thinner region within a frame region for leads lines and bond pads. The conductive sheet is etched to form a plurality of bond pads in a first level of the thinner region arranged in at least a first row and a second row. Each bond pad has a pad width and is separated from an adjacent bond pad by a bond pad clearance distance. The conductive sheet is etched from an opposite side to form a plurality of lead lines in a second level of the thinner region having a line width and is separated from an adjacent lead line by at least a lead line clearance distance. Each bond pad of the second plurality of bond pads is connected to one of the plurality of lead lines on the second level that is routed between adjacent bond pads in the first row, so that the lead lines are routed on a different level from the bond pads.

Abstract translation: 提供一种用于形成用于集成电路的多电平引线框架的方法。 从一侧蚀刻导电片，以在用于引线和接合焊盘的框架区域内形成更薄的区域。 蚀刻导电片以在布置在至少第一行和第二行中的较薄区域的第一级中形成多个接合焊盘。 每个接合焊盘具有焊盘宽度，并且通过接合焊盘间隙距离与相邻接合焊盘分离。 导电片从相对侧蚀刻，以在具有线宽的较薄区域的第二级中形成多条引线，并且与相邻引线相隔至少一条引线间隙距离。 第二多个接合焊盘中的每个接合焊盘连接到第二级上的多条引线之一，该引线在第一行中的相邻接合焊盘之间布线，使得引线在与焊接不同的层级上布线 垫