公开(公告)号：US20170162674A1

公开(公告)日：2017-06-08

申请号：US15355781

申请日：2016-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum KIM ,  Kang Hun MOON ,  Choeun LEE ,  Kyung Yub JEON ,  Sujin JUNG ,  Haegeon JUNG ,  Yang XU

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a ‘U’-shaped section; and forming source/drain regions in the recess regions.

公开(公告)号：US20220415905A1

公开(公告)日：2022-12-29

申请号：US17929513

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Myung-Gil KANG ,  Kang-Hun MOON ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Min-Hee CHOI ,  Yang XU ,  Dong-Suk SHIN ,  Kwan-Heum LEE ,  Hoi-Sung CHUNG

IPC: H01L27/11 ,  H01L23/528 ,  H01L29/66 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L23/485 ,  H01L27/092 ,  H01L29/165

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20220159321A1

公开(公告)日：2022-05-19

申请号：US17530625

申请日：2021-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yang XU ,  Wei HUANG ,  Siyuan HUANG

IPC: H04N21/2343 ,  H04N21/234 ,  H04N19/40 ,  H04N19/154 ,  H04N19/105 ,  H04N19/172

Abstract: Disclosed is a content sharing method, an electronic device and a non-transitory computer-readable storage medium, wherein the content sharing method includes: receiving a target video, determining a type of video sharing based on the target video not being a High Dynamic Range 10+ (HDR10+) standard video, selectively transcoding the target video to a different standard video based on whether the determined type of video sharing is a real-time video sharing, and sending the transcoded target video to a target receiver.

公开(公告)号：US20210143049A1

公开(公告)日：2021-05-13

申请号：US17137485

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Seokhoon KIM ,  Seung Hun LEE ,  Yang XU ,  Jeongho YOO ,  Jongryeol YOO ,  Youngdae CHO

IPC: H01L21/762 ,  H01L21/225 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active fin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin

公开(公告)号：US20200328290A1

公开(公告)日：2020-10-15

申请号：US16686378

申请日：2019-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUN KWAN YU ,  Seung Hun LEE ,  Yang XU

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/201 ,  H01L29/165

Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.

公开(公告)号：US20160359021A1

公开(公告)日：2016-12-08

申请号：US15134556

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum KIM ,  Kang Hun MOON ,  Choeun LEE ,  Sujin JUNG ,  Yang XU

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L29/06 ,  H01L21/308 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

Abstract translation: 提供了形成集成电路器件的方法。 所述方法可以包括在衬底上形成栅极结构，在栅极结构的侧壁上形成第一蚀刻掩模，使用栅极结构和第一蚀刻掩模各向异性蚀刻衬底作为蚀刻掩模，以在衬底中形成预备凹槽 在所述初步凹槽中形成牺牲层，在所述第一蚀刻掩模上形成第二蚀刻掩模，使用所述栅极结构和所述第一和第二蚀刻掩模作为蚀刻掩模蚀刻所述牺牲层和所述牺牲层下方的所述衬底，以形成 源极/漏极凹部，并且在源极/漏极凹部中形成源极/漏极。 源极/漏极凹部的侧壁可以相对于第二蚀刻掩模的外表面朝向栅极结构凹陷。