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    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    11.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200303390A1

    公开(公告)日：2020-09-24

    申请号：US16782737

    申请日：2020-02-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sejun Park ,  Jaeduk Lee ,  Jaehoon Jang ,  Jin-Kyu Kang ,  Seungwan Hong ,  Okcheon Hong

    IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/02

    Abstract: A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

    Three-dimensional semiconductor memory device and method of operating the same
    12.
    发明授权
    Three-dimensional semiconductor memory device and method of operating the same 有权

    公开(公告)号：US10396093B2

    公开(公告)日：2019-08-27

    申请号：US15714254

    申请日：2017-09-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minyeong Song ,  Chadong Yeo ,  Jaeduk Lee ,  Jaehoon Jang

    IPC: H01L27/11582 ,  H01L27/11565 ,  G11C16/12 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/10

    Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode structure including a plurality of cell electrodes vertically stacked on a substrate and extending in a first direction, lower and upper string selection electrodes sequentially stacked on the electrode structure, a first vertical structure penetrating the lower and upper string selection electrodes and the electrode structure, a second vertical structure spaced apart from the upper string selection electrode and penetrating the lower string selection electrode and the electrode structure, and a first bit line intersecting the electrode structure and extending in a second direction different from the first direction. The first bit line is connected in common to the first and second vertical structures. The second vertical structure does not extend through the upper string selection electrode.

    Three-Dimensional Semiconductor Device and Method for Fabricating the Same
    13.
    发明申请
    Three-Dimensional Semiconductor Device and Method for Fabricating the Same 有权
    三维半导体器件及其制造方法

    公开(公告)号：US20130295761A1

    公开(公告)日：2013-11-07

    申请号：US13933772

    申请日：2013-07-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    IPC: H01L21/768

    CPC classification number: H01L21/768 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

    Abstract: Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.

    Abstract translation: 提供一种三维半导体器件及其制造方法。 该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。 第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。 第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。 这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES
    14.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICES 有权
    三维半导体器件

    公开(公告)号：US20130161831A1

    公开(公告)日：2013-06-27

    申请号：US13771526

    申请日：2013-02-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

    IPC: H01L23/522

    CPC classification number: H01L21/768 ,  H01L23/5226 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed.

    Abstract translation: 三维半导体器件可以包括在基板的布线和接触区域上包括布线和接触区域以及薄膜结构的基板。 薄膜结构可以包括在接触区域中限定梯形结构的多个交替布线层和层间绝缘层，使得每个布线层包括在接触区域中延伸超过其它布线层的接触表面 离衬底更远。 多个接触结构可以在垂直于衬底的表面的方向上延伸，其中每个接触结构电连接到相应的一个接线层的接触表面。 还讨论了相关方法。

    Operating methods of nonvolatile memory devices including a ground select transistor and first and second dummy memory cells
    16.
    发明授权
    Operating methods of nonvolatile memory devices including a ground select transistor and first and second dummy memory cells 有权
    包括接地选择晶体管和第一和第二虚拟存储器单元的非易失性存储器件的操作方法

    公开(公告)号：US09548123B2

    公开(公告)日：2017-01-17

    申请号：US14820703

    申请日：2015-08-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byeong-In Choe ,  Jaehoon Jang ,  Kihyun Kim ,  Sunil Shim ,  Woonkyung Lee

    IPC: G11C16/00 ,  G11C7/00 ,  H01L29/00 ,  H01L27/11 ,  G11C16/14 ,  G11C7/14 ,  G11C16/04 ,  G11C16/30 ,  H01L29/792 ,  H01L27/115 ,  G11C16/10 ,  G11C16/16

    CPC classification number: G11C16/14 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/11582 ,  H01L29/7926

    Abstract: A nonvolatile memory device includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the cell strings; floating ground selection lines connected to ground selection transistors of the cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.

    Abstract translation: 非易失性存储器件包括衬底和设置在衬底上的多个单元串，每个单元串包括沿垂直于衬底的方向堆叠的多个存储单元。 所述方法可以包括将字线擦除电压施加到连接到所述单元串的存储单元的字线; 连接到单元串的地选择晶体管的浮动接地选择线和连接到多个单元串的串选择晶体管的串选择线; 将至少一个连接到所述多个单元串中的每一个的存储单元之间的至少一个下部虚设存储单元和所述多个单元串中的接地选择晶体管的下虚拟字线施加接地电压; 向基板施加擦除电压; 并且在施加擦除电压之后浮置所述至少一个下部虚拟字线。

    Three-dimensional nonvolatile memory and operating method of three-dimensional nonvolatile memory
    18.
    发明授权
    Three-dimensional nonvolatile memory and operating method of three-dimensional nonvolatile memory 有权
    三维非易失性存储器和三维非易失性存储器的操作方法

    公开(公告)号：US09412450B2

    公开(公告)日：2016-08-09

    申请号：US14155877

    申请日：2014-01-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gilsung Lee ,  Jaehoon Jang ,  Kihyun Kim ,  Sunil Shim

    IPC: G11C11/34 ,  G11C16/04 ,  G11C16/26

    CPC classification number: G11C16/0483 ,  G11C16/26

    Abstract: Disclosed is a nonvolatile memory having a memory cell array including a plurality of cell strings, each cell string including memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor between the memory cells and the substrate, and a string selection transistor between the memory cells and a bit line. The memory also includes an address decoder connected to the memory cells, the string selection transistors, and the ground selection transistors, and configured to apply a ground voltage to the string selection lines, word lines, and ground selection line. Further, the memory includes a read/write circuit connected to the string selection transistors through bit lines, and at least one first memory cell maintains a threshold voltage higher than a threshold voltage distribution corresponding to an erase state.

    Abstract translation: 公开了具有包括多个单元串的存储单元阵列的非易失性存储器，每个单元串包括沿垂直于衬底的方向堆叠的存储单元，存储单元和衬底之间的接地选择晶体管，以及串选择晶体管， 存储单元和位线。 存储器还包括连接到存储单元的地址解码器，串选择晶体管和接地选择晶体管，并且被配置为对串选择线，字线和地选择线施加接地电压。 此外，存储器包括通过位线连接到串选择晶体管的读/写电路，并且至少一个第一存储单元维持高于对应于擦除状态的阈值电压分布的阈值电压。

    Nonvolatile memory devices having a three dimensional structure utilizing strapping of a common source region and/or a well region
    19.
    发明授权
    Nonvolatile memory devices having a three dimensional structure utilizing strapping of a common source region and/or a well region 有权
    具有利用公共源区和/或阱区的绑带的三维结构的非易失性存储器件

    公开(公告)号：US09219072B2

    公开(公告)日：2015-12-22

    申请号：US14548557

    申请日：2014-11-20

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

    IPC: H01L27/115 ,  H01L23/522

    CPC classification number: H01L27/11578 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11582

    Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

    Abstract translation: 具有三维结构的非易失性存储装置。 非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

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