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    Three-dimensional semiconductor memory device
    1.
    发明授权
    Three-dimensional semiconductor memory device 审中-公开

    公开(公告)号：US10672792B2

    公开(公告)日：2020-06-02

    申请号：US16266409

    申请日：2019-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kangyoon Choi ,  Gilsung Lee ,  Dong-Sik Lee ,  Yongsik Yim ,  Eunsuk Cho

    IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/28

    Abstract: Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.

    Three-dimensional nonvolatile memory and operating method of three-dimensional nonvolatile memory
    4.
    发明授权
    Three-dimensional nonvolatile memory and operating method of three-dimensional nonvolatile memory 有权
    三维非易失性存储器和三维非易失性存储器的操作方法

    公开(公告)号：US09412450B2

    公开(公告)日：2016-08-09

    申请号：US14155877

    申请日：2014-01-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gilsung Lee ,  Jaehoon Jang ,  Kihyun Kim ,  Sunil Shim

    IPC: G11C11/34 ,  G11C16/04 ,  G11C16/26

    CPC classification number: G11C16/0483 ,  G11C16/26

    Abstract: Disclosed is a nonvolatile memory having a memory cell array including a plurality of cell strings, each cell string including memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor between the memory cells and the substrate, and a string selection transistor between the memory cells and a bit line. The memory also includes an address decoder connected to the memory cells, the string selection transistors, and the ground selection transistors, and configured to apply a ground voltage to the string selection lines, word lines, and ground selection line. Further, the memory includes a read/write circuit connected to the string selection transistors through bit lines, and at least one first memory cell maintains a threshold voltage higher than a threshold voltage distribution corresponding to an erase state.

    Abstract translation: 公开了具有包括多个单元串的存储单元阵列的非易失性存储器，每个单元串包括沿垂直于衬底的方向堆叠的存储单元，存储单元和衬底之间的接地选择晶体管，以及串选择晶体管， 存储单元和位线。 存储器还包括连接到存储单元的地址解码器，串选择晶体管和接地选择晶体管，并且被配置为对串选择线，字线和地选择线施加接地电压。 此外，存储器包括通过位线连接到串选择晶体管的读/写电路，并且至少一个第一存储单元维持高于对应于擦除状态的阈值电压分布的阈值电压。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190371808A1

    公开(公告)日：2019-12-05

    申请号：US16266409

    申请日：2019-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kangyoon Choi ,  Gilsung Lee ,  Dong-Sik Lee ,  Yongsik Yim ,  Eunsuk Cho

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/28

    Abstract: Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.

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