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    Semiconductor memory devices and methods of fabricating the same
    2.
    发明授权
    Semiconductor memory devices and methods of fabricating the same 有权

    公开(公告)号：US11107828B2

    公开(公告)日：2021-08-31

    申请号：US16902575

    申请日：2020-06-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Min Hwang ,  Joon-Sung Lim ,  Eunsuk Cho

    IPC: H01L27/11573 ,  H01L27/1157 ,  H01L25/065 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11582 ,  H01L27/11575

    Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.

    Three-dimensional semiconductor memory device
    3.
    发明授权
    Three-dimensional semiconductor memory device 审中-公开

    公开(公告)号：US10672792B2

    公开(公告)日：2020-06-02

    申请号：US16266409

    申请日：2019-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kangyoon Choi ,  Gilsung Lee ,  Dong-Sik Lee ,  Yongsik Yim ,  Eunsuk Cho

    IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/28

    Abstract: Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.

    Nonvolatile memory device and an erasing method thereof
    5.
    发明授权
    Nonvolatile memory device and an erasing method thereof 有权
    非易失性存储器件及其擦除方法

    公开(公告)号：US09558834B2

    公开(公告)日：2017-01-31

    申请号：US14887454

    申请日：2015-10-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byeong-In Choe ,  Mincheol Park ,  Dongseog Eun ,  Eunsuk Cho

    IPC: G11C16/04 ,  G11C16/14 ,  G11C7/04 ,  G11C16/32

    CPC classification number: G11C16/14 ,  G11C7/04 ,  G11C16/32

    Abstract: An erase method of a nonvolatile memory device includes applying an erase voltage to a substrate; sensing a temperature of a memory cell array; setting a delay time based on the temperature of the memory cell array, wherein the delay time starts in response to the erase voltage being applied to the substrate; applying a ground voltage to a ground selection line connected to a ground selection transistor during the delay time; and increasing a voltage of the ground selection line after the delay time.

    Abstract translation: 非易失性存储器件的擦除方法包括向衬底施加擦除电压; 感测存储单元阵列的温度; 基于所述存储单元阵列的温度来设置延迟时间，其中所述延迟时间响应于所述擦除电压被施加到所述衬底而开始; 在延迟时间内将接地电压施加到接地选择晶体管的接地选择线; 并在延迟时间后增加接地选择线的电压。

    Semiconductor memory devices and methods of fabricating the same
    7.
    发明授权
    Semiconductor memory devices and methods of fabricating the same 有权

    公开(公告)号：US10727244B2

    公开(公告)日：2020-07-28

    申请号：US15982001

    申请日：2018-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Min Hwang ,  Joon-Sung Lim ,  Eunsuk Cho

    IPC: H01L27/115 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11582 ,  H01L25/065 ,  H01L27/11575

    Abstract: A semiconductor memory device includes a first semiconductor chip and a second semiconductor chip. Each semiconductor chip of the first and second semiconductor chips may include a cell array region and a peripheral circuit region. The cell array region may include an electrode structure including electrodes sequentially stacked on a body conductive layer and vertical structures extending through the electrode structure and connected to the body conductive layer. The peripheral circuit region may include a residual substrate on the body conductive layer and on which a peripheral transistor is located. A bottom surface of the body conductive layer of the second semiconductor chip may face a bottom surface of the body conductive layer of the first semiconductor chip.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190371808A1

    公开(公告)日：2019-12-05

    申请号：US16266409

    申请日：2019-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kangyoon Choi ,  Gilsung Lee ,  Dong-Sik Lee ,  Yongsik Yim ,  Eunsuk Cho

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/28

    Abstract: Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.

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