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    Semiconductor devices and methods of manufacturing the same
    11.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权

    公开(公告)号：US10068993B2

    公开(公告)日：2018-09-04

    申请号：US15871479

    申请日：2018-01-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JinBum Kim ,  Kang Hun Moon ,  Choeun Lee ,  Sujin Jung ,  Yang Xu

    IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

    Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

    SEMICONDUCTOR DEVICES
    14.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230420535A1

    公开(公告)日：2023-12-28

    申请号：US18195074

    申请日：2023-05-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kanghun Moon ,  Kyungho Kim ,  Kihwan Kim ,  Choeun Lee ,  Yonguk Jeon

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L29/06 ,  H01L29/775

    CPC classification number: H01L29/42392 ,  H01L29/66545 ,  H01L29/41775 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/775

    Abstract: A semiconductor device includes: an active region on a substrate extending in a first direction; a plurality of semiconductor layers spaced apart from each in a vertical direction on the active region, the plurality of semiconductor layers including lower and upper semiconductor layers; a gate structure on the substrate extending in a second direction to intersect the active region and the plurality of semiconductor layers; and a source/drain region on the active region and contacting the plurality of semiconductor layers. The source/drain region includes first epitaxial layers, including first layers on a side surface of the lower semiconductor layer and a second layer provided on and contacting the active region, and a second epitaxial layer contacts a side surface of the upper semiconductor layer in the first direction, and the first layer is between the second epitaxial layer and the side surface of the lower semiconductor layer.

    Semiconductor device and method of manufacturing the same
    18.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09373703B2

    公开(公告)日：2016-06-21

    申请号：US14499922

    申请日：2014-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JinBum Kim ,  Jungho Yoo ,  Byeongchan Lee ,  Choeun Lee ,  Hyun Jung Lee ,  Seong Hoon Jeong ,  Bonyoung Koo

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/165

    CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

    Abstract: A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.

    Abstract translation: 一种制造半导体器件的方法包括形成从半导体衬底突出的有源图案，形成与有源图案交叉的伪栅极图案，在伪栅极图案的相对的第一和第二侧壁上形成栅极间隔物，将伪栅极图案去除 形成栅极区域，暴露栅极间隔件之间的有源图案的上表面和侧壁，凹陷由栅极区域暴露的有源图案的上表面，以形成通道凹槽区域，在通道凹槽区域中形成通道图案 选择性外延生长（SEG）工艺，以及顺序地形成覆盖栅极区域中的沟道图案的上表面和侧壁的栅极电介质层和栅电极。 沟道图案具有与半导体衬底不同的晶格常数。

    SEMICONDUCTOR DEVICE
    20.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220059654A1

    公开(公告)日：2022-02-24

    申请号：US17207690

    申请日：2021-03-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinbum Kim ,  Seokhoon Kim ,  Kwanheum Lee ,  Choeun Lee ,  Sujin Jung

    IPC: H01L29/08 ,  H01L29/78 ,  H01L29/167 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

    Abstract: A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.

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