公开(公告)号：US20160027902A1

公开(公告)日：2016-01-28

申请号：US14805876

申请日：2015-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jieon Yoon ,  Seokhoon Kim ,  Gyeom Kim ,  Nam-Kyu Kim ,  JinBum Kim ,  Dong Chan Suh ,  Kwan Heum Lee ,  Byeongchan Lee ,  Choeun Lee ,  Sujin Jung

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L29/04 ,  H01L21/265

CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a gate pattern on a semiconductor substrate, injecting amorphization elements into the semiconductor substrate to form an amorphous portion at a side of the gate pattern, removing the amorphous portion to form a recess region, and forming a source/drain pattern in the recess region. When the recess region is formed, an etch rate of the amorphous portion is substantially the same in two different directions (e.g., and any other direction) of the semiconductor substrate.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在半导体衬底上形成栅极图案，将非晶化元件注入到半导体衬底中以在栅极图案的一侧形成非晶部分，去除非晶部分以形成凹陷区域，并且形成源极/漏极图案 凹陷区域。 当形成凹陷区域时，非晶部分的蚀刻速率在半导体衬底的两个不同方向（例如，<111>和任何其它方向）上基本相同。

公开(公告)号：US10319859B2

公开(公告)日：2019-06-11

申请号：US15844863

申请日：2017-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujin Jung ,  JinBum Kim ,  Kang Hun Moon ,  Kwan Heum Lee ,  Byeongchan Lee ,  Choeun Lee ,  Yang Xu

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.

公开(公告)号：US09252244B2

公开(公告)日：2016-02-02

申请号：US14498996

申请日：2014-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum Kim ,  Seong Hoon Jeong ,  Jeon Il Lee ,  Seokhoon Kim ,  Kwan Heum Lee ,  Choeun Lee ,  Yu-Jin Pyo

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/51 ,  H01L29/161 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/12

CPC classification number: H01L29/66795 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern.

Abstract translation: 本发明构思提供制造半导体器件的方法。 该方法包括图案化衬底以形成有源图案，形成与有源图案相交的栅极图案，在栅极图案的侧壁上形成栅极间隔物，形成覆盖栅极图案的上部区域的生长抑制层，以及形成 源极/漏极在栅极图案的相对的第一和第二侧。

公开(公告)号：US11380541B2

公开(公告)日：2022-07-05

申请号：US17006799

申请日：2020-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Dongwoo Kim ,  Jihye Yi ,  JinBum Kim ,  Sangmoon Lee ,  Seunghun Lee

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66 ,  H01L23/532 ,  H01L23/485 ,  H01L29/10 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L21/28

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source/drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region, on the channel region; a contact structure on the source/drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source/drain region includes a first epitaxial region having a recessed surface and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extended portion, extended from a portion overlapping the contact structure in a vertical direction, in a horizontal direction and overlapping the contact spacer in the vertical direction.

公开(公告)号：US09905676B2

公开(公告)日：2018-02-27

申请号：US15134556

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum Kim ,  Kang Hun Moon ,  Choeun Lee ,  Sujin Jung ,  Yang Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

公开(公告)号：US20160322495A1

公开(公告)日：2016-11-03

申请号：US15138840

申请日：2016-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kanghun Moon ,  JinBum Kim ,  Kwan Heum Lee ,  Choeun Lee ,  Sujin Jung ,  Yang Xu

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/165 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes an active pattern protruding from a substrate and extending in a first direction, first and second gate electrodes intersecting the active pattern in a second direction intersecting the first direction, and a source/drain region disposed on the active pattern between the first and second gate electrodes. The source/drain region includes a first part adjacent to an uppermost surface of the active pattern and provided at a level lower than the uppermost surface of the active pattern, and a second part disposed under the first part so as to be in contact with the first part. A width of the first part along the first direction decreases in a direction away from the substrate, and a width of the second part along the first direction increases in a direction away from the substrate.

Abstract translation: 半导体器件包括从衬底突出并沿第一方向延伸的有源图案，在与第一方向相交的第二方向上与有源图案相交的第一和第二栅电极以及设置在第一和第二方向上的有源图案之间的源/漏区域 和第二栅电极。 源极/漏极区域包括与有源图案的最上表面相邻并且设置在比有源图案的最上表面低的水平面处的第一部分，以及设置在第一部分下方以与第一部分接触的第二部分 第一部分。 沿着第一方向的第一部分的宽度沿离开基板的方向减小，并且沿着第一方向的第二部分的宽度在远离基板的方向上增加。

公开(公告)号：US09530870B2

公开(公告)日：2016-12-27

申请号：US14805876

申请日：2015-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jieon Yoon ,  Seokhoon Kim ,  Gyeom Kim ,  Nam-Kyu Kim ,  JinBum Kim ,  Dong Chan Suh ,  Kwan Heum Lee ,  Byeongchan Lee ,  Choeun Lee ,  Sujin Jung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/04 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a gate pattern on a semiconductor substrate, injecting amorphization elements into the semiconductor substrate to form an amorphous portion at a side of the gate pattern, removing the amorphous portion to form a recess region, and forming a source/drain pattern in the recess region. When the recess region is formed, an etch rate of the amorphous portion is substantially the same in two different directions (e.g., and any other direction) of the semiconductor substrate.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在半导体衬底上形成栅极图案，将非晶化元件注入到半导体衬底中以在栅极图案的一侧形成非晶部分，去除非晶部分以形成凹陷区域，并且形成源极/漏极图案 凹陷区域。 当形成凹陷区域时，非晶部分的蚀刻速率在半导体衬底的两个不同方向（例如，<111>和任何其它方向）上基本相同。

公开(公告)号：US09412731B2

公开(公告)日：2016-08-09

申请号：US14562788

申请日：2014-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhoon Kim ,  Bonyoung Koo ,  JinBum Kim ,  Chul Kim ,  Kwan Heum Lee ,  Byeongchan Lee ,  Sujin Jung

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a semiconductor device which includes a substrate including a first region and a second region different from the first region, a first active pattern provided on the substrate in the first region, a second active pattern provided on the substrate in the second region, a first gate structure crossing over the first active pattern and a second gate structure crossing over the second active pattern, first source/drain regions disposed on the first active pattern at opposite sides of the first gate structure, second source/drain regions disposed on the second active pattern at opposite sides of the second gate structure, and auxiliary spacers disposed in the first region to cover a lower portion of each of the first source/drain regions.

Abstract translation: 提供一种半导体器件，其包括：衬底，其包括第一区域和与第一区域不同的第二区域;设置在第一区域中的衬底上的第一有源图案，设置在第二区域中的衬底上的第二有源图案; 在第一有源图案上交叉的第一栅极结构和与第二有源图案交叉的第二栅极结构，在第一栅极结构的相对侧设置在第一有源图案上的第一源/漏区，设置在第二有源图案上的第二栅极结构的第二栅极结构 在第二栅极结构的相对侧的有源图案以及设置在第一区域中以覆盖每个第一源极/漏极区域的下部的辅助间隔物。

公开(公告)号：US09373703B2

公开(公告)日：2016-06-21

申请号：US14499922

申请日：2014-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum Kim ,  Jungho Yoo ,  Byeongchan Lee ,  Choeun Lee ,  Hyun Jung Lee ,  Seong Hoon Jeong ,  Bonyoung Koo

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.

Abstract translation: 一种制造半导体器件的方法包括形成从半导体衬底突出的有源图案，形成与有源图案交叉的伪栅极图案，在伪栅极图案的相对的第一和第二侧壁上形成栅极间隔物，将伪栅极图案去除 形成栅极区域，暴露栅极间隔件之间的有源图案的上表面和侧壁，凹陷由栅极区域暴露的有源图案的上表面，以形成通道凹槽区域，在通道凹槽区域中形成通道图案 选择性外延生长（SEG）工艺，以及顺序地形成覆盖栅极区域中的沟道图案的上表面和侧壁的栅极电介质层和栅电极。 沟道图案具有与半导体衬底不同的晶格常数。

公开(公告)号：US20210151319A1

公开(公告)日：2021-05-20

申请号：US17006799

申请日：2020-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Dongwoo Kim ,  Jihye Yi ,  JinBum Kim ,  Sangmoon Lee ,  Seunghun Lee

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source/drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region, on the channel region; a contact structure on the source/drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source/drain region includes a first epitaxial region having a recessed surface and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extended portion, extended from a portion overlapping the contact structure in a vertical direction, in a horizontal direction and overlapping the contact spacer in the vertical direction.