公开(公告)号：US11355489B2

公开(公告)日：2022-06-07

申请号：US17009941

申请日：2020-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounggon Kang ,  Subin Jin ,  Ha-Young Kim

IPC: H01L27/02 ,  H03K3/3562 ,  H03K3/037 ,  H01L27/118

Abstract: A semiconductor device includes a standard cell, which includes first to fourth active areas that are extended in a first direction, first to fourth gate lines that are extended in a second direction perpendicular to the first direction over the first to fourth active areas and are disposed parallel to each other, a first cutting layer that is disposed between the first active area and the second active area and separates the second and third gate lines, a second cutting layer that is disposed between the third active area and the fourth active area and separates the second and third gate lines, a first gate contact that is formed on the second gate line separated by the first cutting layer and the second cutting layer, and a second gate contact that is formed on the third gate line separated by the first cutting layer and the second cutting layer.

公开(公告)号：US20220108989A1

公开(公告)日：2022-04-07

申请号：US17219175

申请日：2021-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounggon Kang ,  Taejun Yoo ,  Seunghyun Yang ,  Dalhee Lee

IPC: H01L27/11 ,  H01L23/528 ,  G11C11/417 ,  G11C11/412

Abstract: A semiconductor device is provided. The semiconductor device includes power supply lines extending in a first direction; first transistors, each of which is formed in a first region and has a first threshold voltage; and second transistors, each of which is formed in a second region and has a second threshold voltage higher than the first threshold voltage. One of the plurality of power supply lines is interposed between the first region and the second region, the first transistors implement a first portion of a multiplexer, a clock buffer and a first latch that are disposed on a data path, the second transistors implement a second portion of the multiplexer circuit and a second latch that are disposed on a feedback path, and the first portion of the multiplexer circuit and the second portion of the multiplexer circuit are disposed in a common location along the first direction.

公开(公告)号：US20240266290A1

公开(公告)日：2024-08-08

申请号：US18433327

申请日：2024-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounggon Kang

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/4175 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit includes a substrate and a plurality of standard cells on the substrate. A standard cell of the plurality of standard cells includes a backside wiring pattern arranged on a lower portion of the substrate and including at least an internal connection node of the standard cell and a plurality of gate lines arranged on an upper portion of the substrate and extending in a first horizontal direction. At least one of the plurality of gate lines functions as an input pin of the standard cell.

公开(公告)号：US12044733B2

公开(公告)日：2024-07-23

申请号：US18194643

申请日：2023-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounggon Kang ,  Dalhee Lee ,  Giyoung Yang ,  Minji Kim ,  Taejung Seol ,  Jaebeom Yang

IPC: G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/318525 ,  G01R31/31725 ,  G01R31/318541

Abstract: A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.

公开(公告)号：US20240137012A1

公开(公告)日：2024-04-25

申请号：US18373017

申请日：2023-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounggon Kang ,  Dalhee Lee

IPC: H03K3/037 ,  G06F1/08 ,  H03K19/20

CPC classification number: H03K3/037 ,  G06F1/08 ,  H03K19/20 ,  H03K3/012

Abstract: A clock gating cell is provided. The clock gating cell includes: an inverter circuit configured to generate an inverted clock signal by inverting a clock signal; a first control circuit configured to receive the inverted clock signal, an enable signal, and a scan enable signal, and output a first internal signal at a first node; a second control circuit configured to receive the first internal signal, the clock signal, the enable signal, and the scan enable signal, and output a second internal signal at a second node; and an output driver configured to receive the second internal signal, and output an output clock signal to an output node and a third internal signal to a third node. The first control circuit and the second control circuit are configured to receive the third internal signal at the third node.

公开(公告)号：US11699992B2

公开(公告)日：2023-07-11

申请号：US16726379

申请日：2019-12-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jintae Kim ,  Byounggon Kang ,  Changbeom Kim ,  Ha-Young Kim ,  Yongeun Cho

IPC: H03K3/037 ,  H01L27/02 ,  H01L23/528 ,  H01L29/06 ,  H01L27/092 ,  H01L23/522 ,  H01L29/423

CPC classification number: H03K3/0372 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a flip flop cell. The flip flop cell is formed on a semiconductor substrate, includes a flip flop circuit, and comprises a scan mux circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan mux circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices which together output a resulting signal for that circuit based on inputs, is a sub-circuit of the flip flop circuit, and occupies a continuously-bounded area of the flip flop circuit from a plan view. At least a first sub-circuit and a second sub-circuit of the sub-circuits overlap from the plan view in a first overlap region, the first overlap region including part of a first continuously-bounded area for the first sub-circuit and part of a second continuously-bounded area for the second sub-circuit.

公开(公告)号：US20220367439A1

公开(公告)日：2022-11-17

申请号：US17722004

申请日：2022-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounggon Kang

IPC: H01L27/02

Abstract: An integrated circuit includes plural standard cells performing a same function. The standard cells include a first standard cell and a second standard cell, and the first standard cell and the second standard cell are to the same as each other in terms of an arrangement of internal conductive patterns and are different from each other in terms of a position of a via formed over a gate line through which an input signal is input.