公开(公告)号：US20220028455A1

公开(公告)日：2022-01-27

申请号：US17382322

申请日：2021-07-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yohei SAWADA ,  Masao MORIMOTO ,  Makoto YABUUCHI

IPC: G11C15/04

Abstract: The plurality of CAM cells MC are configured to discriminate a match or mismatch between stored data stored in advance and search data. A match line is coupled to a plurality of CAM cells, and has a voltage level controlled based on discrimination results of the plurality of CAM cells. A first transistor and a second transistor are coupled in series between a common match output line and a predetermined power source. The first transistor is controlled to be turned ON or OFF based on a voltage level of the match line, and the second transistor is controlled to be turned ON or OFF by a search enabling signal asserted at the time of a search operation.

公开(公告)号：US20210375362A1

公开(公告)日：2021-12-02

申请号：US17318632

申请日：2021-05-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto YABUUCHI

IPC: G11C15/04 ,  G11C7/06 ,  G11C7/12 ,  G11C8/08

Abstract: A semiconductor device includes a plurality of memory cells connected to a match line; a word line driver connected to a word line; a valid cell configured to store a valid bit indicating valid or invalid of an entry; a first precharge circuit connected to one end of the match line and configured to precharge the match line to a high level; and a second precharge circuit connected to the other end of the match line and configured to precharge the match line to a high level. The plurality of memory cells are arranged between the first precharge circuit and the second precharge circuit, and the second precharge circuit is arranged between the word line driver and the plurality of memory cells.

公开(公告)号：US20200342936A1

公开(公告)日：2020-10-29

申请号：US16845929

申请日：2020-04-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshisato YOKOYAMA ,  Makoto YABUUCHI

IPC: G11C11/418 ,  G11C11/419

Abstract: A semiconductor device includes a first wiring having a first portion, a second portion, a third portion provided between the first portion and the second portion, memory cells connected to the third portion of the first wiring, a field effect transistor having a drain connected to the second portion, and a gate, and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion located nearest to the first portion and a fifth portion located nearest to the second portion. The first wiring further includes a sixth portion disposed between the first portion and the fourth portion. The memory cells include a first memory cell connected to the fourth portion and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.

公开(公告)号：US20190378831A1

公开(公告)日：2019-12-12

申请号：US16544101

申请日：2019-08-19

Applicant: Renesas Electronics Corporation

Inventor： Takeshi OKAGAKI ,  Koji SHIBUTANI ,  Makoto YABUUCHI ,  Nobuhiro TSUDA

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

公开(公告)号：US20190189197A1

公开(公告)日：2019-06-20

申请号：US16176299

申请日：2018-10-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Yuichiro ISHII ,  Yohei SAWADA ,  Makoto YABUUCHI

IPC: G11C11/419 ,  G11C11/412

Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.

公开(公告)号：US20180240513A1

公开(公告)日：2018-08-23

申请号：US15957263

申请日：2018-04-19

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Ken SHIBATA ,  Shinji TANAKA ,  Makoto YABUUCHI ,  Noriaki MAEDA

IPC: G11C11/419 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

公开(公告)号：US20170263605A1

公开(公告)日：2017-09-14

申请号：US15607599

申请日：2017-05-29

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI

IPC: H01L27/088 ,  H01L27/06 ,  H01L27/02 ,  G11C7/10

CPC classification number: H01L27/0886 ,  G11C7/10 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0924

Abstract: Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.

公开(公告)号：US20160049395A1

公开(公告)日：2016-02-18

申请号：US14826730

申请日：2015-08-14

Applicant: Renesas Electronics Corporation

Inventor： Takeshi OKAGAKI ,  Koji SHIBUTANI ,  Makoto YABUUCHI ,  Nobuhiro TSUDA

IPC: H01L27/088

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L27/0924 ,  H01L29/41791

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract translation: 可以减少具有FINFET的半导体器件的区域。 n沟道FINFET和p沟道FINFET的漏极区域由栅极电极和与其相邻的虚拟栅极之间的第二Y栅极的两个第二局部互连提取到与​​第二Y栅极相邻的第三Y栅格。 这些第二局部互连通过在第三Y格中沿X方向延伸的第一局部互连连接。 根据这种单元布局，由于第一局部互连的布置，网格的数量增加了一个，所以可以减小X方向上的长度。 结果，可以减小单元单元的单元面积，同时确保第一和第二局部互连之间的空间。

公开(公告)号：US20140016391A1

公开(公告)日：2014-01-16

申请号：US14026575

申请日：2013-09-13

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA ,  Makoto YABUUCHI ,  Yuta YOSHIDA

IPC: G11C5/06

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C11/418

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract translation: 提供了具有减小操作时序的变化的存储单元的半导体器件。 例如，半导体器件设置有与适当的位线相对布置的虚拟位线，以及顺序耦合到虚拟位线的列方向负载电路。 每个列方向负载电路设置有多个固定在截止状态的NMOS晶体管，其中预定的NMOS晶体管具有适当地耦合到任何虚拟位线的源极和漏极。 将与预定NMOS晶体管的扩散层电容相关的负载电容加到虚拟位线，并且对应于负载电容，建立从解码激活信号到虚拟位线信号的延迟时间。 当设置读出放大器的启动定时时，采用虚拟位线信号。

公开(公告)号：US20190027212A1

公开(公告)日：2019-01-24

申请号：US16143940

申请日：2018-09-27

Applicant: Renesas Electronics Corporation

Inventor： Yohei SAWADA ,  Makoto YABUUCHI ,  Yuichiro ISHII

IPC: G11C11/417 ,  G11C11/413 ,  G11C11/412 ,  G11C11/41 ,  G11C5/14

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413

Abstract: A semiconductor device includes a SRAM (Static Random Access Memory) circuit. The SRAM circuit includes a static memory cell, a word line coupled with the static memory cell, a pair of bit lines coupled with the static memory cell, a first interconnection coupled with the static memory cell, and supplying a first potential, a second interconnection coupled with the static memory cell, and supplying a second potential lower than the first potential, a first potential control circuit controlling a potential of the second interconnection, and a second potential control circuit controlling a potential of the first interconnection. The SRAM circuit includes, as an operation mode a first operation mode for reading data from the SRAM circuit, or for writing data into the SRAM circuit, and a second operation mode for reducing power consumption than the first operation mode.