公开(公告)号：US20190378831A1

公开(公告)日：2019-12-12

申请号：US16544101

申请日：2019-08-19

Applicant: Renesas Electronics Corporation

Inventor： Takeshi OKAGAKI ,  Koji SHIBUTANI ,  Makoto YABUUCHI ,  Nobuhiro TSUDA

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

公开(公告)号：US20160049395A1

公开(公告)日：2016-02-18

申请号：US14826730

申请日：2015-08-14

Applicant: Renesas Electronics Corporation

Inventor： Takeshi OKAGAKI ,  Koji SHIBUTANI ,  Makoto YABUUCHI ,  Nobuhiro TSUDA

IPC: H01L27/088

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L27/0924 ,  H01L29/41791

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract translation: 可以减少具有FINFET的半导体器件的区域。 n沟道FINFET和p沟道FINFET的漏极区域由栅极电极和与其相邻的虚拟栅极之间的第二Y栅极的两个第二局部互连提取到与​​第二Y栅极相邻的第三Y栅格。 这些第二局部互连通过在第三Y格中沿X方向延伸的第一局部互连连接。 根据这种单元布局，由于第一局部互连的布置，网格的数量增加了一个，所以可以减小X方向上的长度。 结果，可以减小单元单元的单元面积，同时确保第一和第二局部互连之间的空间。

公开(公告)号：US20180350792A1

公开(公告)日：2018-12-06

申请号：US16055728

申请日：2018-08-06

Applicant: Renesas Electronics Corporation

Inventor： Takeshi OKAGAKI ,  Koji SHIBUTANI ,  Makoto YABUUCHI ,  Nobuhiro TSUDA

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L27/0924 ,  H01L29/41791

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

公开(公告)号：US20180026024A1

公开(公告)日：2018-01-25

申请号：US15719830

申请日：2017-09-29

Applicant: Renesas Electronics Corporation

Inventor： Takeshi OKAGAKI ,  Koji SHIBUTANI ,  Makoto YABUUCHI ,  Nobuhiro TSUDA

IPC: H01L27/02 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L27/0924 ,  H01L29/41791

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.