公开(公告)号：US20140239406A1

公开(公告)日：2014-08-28

申请号：US14185801

申请日：2014-02-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuhiro TSUDA ,  Hidekatsu NISHIMAKI ,  Hiroshi OMURA ,  Yuko YOSHIFUKU

IPC: H01L27/092

CPC classification number: H01L27/0928 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11803 ,  H01L27/11898

Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.

Abstract translation: pMIS区域设置在沿第一方向延伸并且穿过多个标准单元和第一外围边缘中的每一个的边界之间。 nMIS区域设置在边界和第二周边边缘之间。 电源布线和接地布线分别沿着第一和第二外围边缘延伸。 多个pMIS布线和多个nMIS布线分别布置在沿着第一方向延伸并且沿第二方向以单个间距布置的多个第一虚拟线和多条第二虚拟线上。 最接近边界的第一虚拟线和最靠近边界的第二虚拟线之间具有大于单个间距的间距。

公开(公告)号：US20180350792A1

公开(公告)日：2018-12-06

申请号：US16055728

申请日：2018-08-06

Applicant: Renesas Electronics Corporation

Inventor： Takeshi OKAGAKI ,  Koji SHIBUTANI ,  Makoto YABUUCHI ,  Nobuhiro TSUDA

IPC: H01L27/02 ,  H01L27/092

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L27/0924 ,  H01L29/41791

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

公开(公告)号：US20160043080A1

公开(公告)日：2016-02-11

申请号：US14808006

申请日：2015-07-24

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya WATANABE ,  Nobuhiro TSUDA

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

Abstract: A semiconductor device is provided which suppresses variations in transistor characteristics such as a source-drain diffusion capacitance. A first transistor TRA is formed in a first element forming area EFA as a divided transistor. A second transistor TRB is formed in a second element forming area EFB as another divided transistor. The first element forming area EFA and the second element forming area EFB are set to the same size. The first element forming area EFA and the second element forming area EFB are arranged deviated from each other in an X direction by a length SPL corresponding to the minimum pitch PT of a gate wiring GH.

Abstract translation: 提供一种半导体器件，其抑制诸如源极 - 漏极扩散电容的晶体管特性的变化。 第一晶体管TRA形成在作为分割晶体管的第一元件形成区域EFA中。 第二晶体管TRB形成在第二元件形成区域EFB中作为另一分割晶体管。 将第一元件形成区域EFA和第二元件形成区域EFB设定为相同的尺寸。 第一元件形成区域EFA和第二元素形成区域EFB被布置在X方向上彼此偏离与栅极布线GH的最小间距PT对应的长度SPL。

公开(公告)号：US20180026024A1

公开(公告)日：2018-01-25

申请号：US15719830

申请日：2017-09-29

Applicant: Renesas Electronics Corporation

Inventor： Takeshi OKAGAKI ,  Koji SHIBUTANI ,  Makoto YABUUCHI ,  Nobuhiro TSUDA

IPC: H01L27/02 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L27/0924 ,  H01L29/41791

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

公开(公告)号：US20190378831A1

公开(公告)日：2019-12-12

申请号：US16544101

申请日：2019-08-19

Applicant: Renesas Electronics Corporation

Inventor： Takeshi OKAGAKI ,  Koji SHIBUTANI ,  Makoto YABUUCHI ,  Nobuhiro TSUDA

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

公开(公告)号：US20160049395A1

公开(公告)日：2016-02-18

申请号：US14826730

申请日：2015-08-14

Applicant: Renesas Electronics Corporation

Inventor： Takeshi OKAGAKI ,  Koji SHIBUTANI ,  Makoto YABUUCHI ,  Nobuhiro TSUDA

IPC: H01L27/088

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L27/0924 ,  H01L29/41791

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract translation: 可以减少具有FINFET的半导体器件的区域。 n沟道FINFET和p沟道FINFET的漏极区域由栅极电极和与其相邻的虚拟栅极之间的第二Y栅极的两个第二局部互连提取到与​​第二Y栅极相邻的第三Y栅格。 这些第二局部互连通过在第三Y格中沿X方向延伸的第一局部互连连接。 根据这种单元布局，由于第一局部互连的布置，网格的数量增加了一个，所以可以减小X方向上的长度。 结果，可以减小单元单元的单元面积，同时确保第一和第二局部互连之间的空间。