公开(公告)号：US20190067428A1

公开(公告)日：2019-02-28

申请号：US16169601

申请日：2018-10-24

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya WATANABE ,  Mitsuru MIYAMORI ,  Katsumi TSUNENO ,  Takashi SHIMIZU

IPC: H01L29/417 ,  H01L29/06

CPC classification number: H01L29/41791 ,  H01L23/5226 ,  H01L29/0657 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/13067 ,  H05K999/99

Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.

公开(公告)号：US20160056154A1

公开(公告)日：2016-02-25

申请号：US14822166

申请日：2015-08-10

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya WATANABE ,  Mitsuru MIYAMORI ,  Katsumi TSUNENO ,  Takashi SHIMIZU

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/41791 ,  H01L23/5226 ,  H01L29/0657 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.

Abstract translation: 所述半导体器件包括：沿X方向平行设置的长方体形状的两个散热片; 并且经由栅极绝缘膜布置在其上并沿Y方向延伸的栅电极被配置如下。 首先，在位于栅电极的一侧的漏极区域上设置排水塞，并在Y方向延伸。 然后，在位于栅极电极的另一侧并在Y方向延伸的源极区域上设置两个源极插头。 此外，排水塞以移位的方式布置，使得其在Y方向上的位置可能不与两个源插头重叠。 根据这样的结构，可以使栅极 - 漏极电容小于栅极 - 源极电容，并且可以抑制基于米勒效应的电路延迟。 此外，与漏极侧的电容相比，源极侧的电容增加，从而提高电路操作的稳定性。

公开(公告)号：US20160043080A1

公开(公告)日：2016-02-11

申请号：US14808006

申请日：2015-07-24

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya WATANABE ,  Nobuhiro TSUDA

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

Abstract: A semiconductor device is provided which suppresses variations in transistor characteristics such as a source-drain diffusion capacitance. A first transistor TRA is formed in a first element forming area EFA as a divided transistor. A second transistor TRB is formed in a second element forming area EFB as another divided transistor. The first element forming area EFA and the second element forming area EFB are set to the same size. The first element forming area EFA and the second element forming area EFB are arranged deviated from each other in an X direction by a length SPL corresponding to the minimum pitch PT of a gate wiring GH.

Abstract translation: 提供一种半导体器件，其抑制诸如源极 - 漏极扩散电容的晶体管特性的变化。 第一晶体管TRA形成在作为分割晶体管的第一元件形成区域EFA中。 第二晶体管TRB形成在第二元件形成区域EFB中作为另一分割晶体管。 将第一元件形成区域EFA和第二元件形成区域EFB设定为相同的尺寸。 第一元件形成区域EFA和第二元素形成区域EFB被布置在X方向上彼此偏离与栅极布线GH的最小间距PT对应的长度SPL。

公开(公告)号：US20180047820A1

公开(公告)日：2018-02-15

申请号：US15796076

申请日：2017-10-27

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya WATANABE ,  Mitsuru MIYAMORI ,  Katsumi TSUNENO ,  Takashi SHIMIZU

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/41791 ,  H01L23/5226 ,  H01L29/0657 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/13067 ,  H05K999/99

Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.

公开(公告)号：US20170154969A1

公开(公告)日：2017-06-01

申请号：US15432463

申请日：2017-02-14

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya WATANABE ,  Mitsuru MIYAMORI ,  Katsumi TSUNENO ,  Takashi SHIMIZU

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L23/5226 ,  H01L29/0657 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.