公开(公告)号：US11189730B2

公开(公告)日：2021-11-30

申请号：US16649716

申请日：2017-12-26

申请人： INTEL CORPORATION

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/161 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

摘要： Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

公开(公告)号：US11004978B2

公开(公告)日：2021-05-11

申请号：US16785431

申请日：2020-02-07

申请人： Intel Corporation

发明人： Glenn Glass ,  Karthik Jambunathan ,  Anand Murthy ,  Chandra Mohapatra ,  Seiyon Kim

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

摘要： Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.

公开(公告)号：US10749032B2

公开(公告)日：2020-08-18

申请号：US16076550

申请日：2016-03-11

申请人： INTEL CORPORATION

发明人： Chandra S. Mohapatra ,  Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Willy Rachmady ,  Gilbert Dewey ,  Tahir Ghani ,  Jack T. Kavalieros

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/775 ,  B82Y10/00 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/20

摘要： Techniques are disclosed for forming transistors including one or more group III-V semiconductor material nanowires using sacrificial group IV semiconductor material layers. In some cases, the transistors may include a gate-all-around (GAA) configuration. In some cases, the techniques may include forming a replacement fin stack that includes group III-V material layer (such as indium gallium arsenide, indium arsenide, or indium antimonide) formed on a group IV material buffer layer (such as silicon, germanium, or silicon germanium), such that the group IV buffer layer can be later removed using a selective etch process to leave the group III-V material for use as a nanowire in a transistor channel. In some such cases, the group III-V material layer may be grown pseudomorphically to the underlying group IV material, so as to not form misfit dislocations. The techniques may be used to form transistors including any number of nanowires.

公开(公告)号：US20200176601A1

公开(公告)日：2020-06-04

申请号：US16785431

申请日：2020-02-07

申请人： Intel Corporation

发明人： Glenn Glass ,  Karthik Jambunathan ,  Anand Murthy ,  Chandra Mohapatra ,  Seiyon Kim

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

摘要： Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.

公开(公告)号：US10510848B2

公开(公告)日：2019-12-17

申请号：US15576150

申请日：2015-06-24

申请人： INTEL CORPORATION

发明人： Glenn A. Glass ,  Ying Pang ,  Anand S. Murthy ,  Tahir Ghani ,  Karthik Jambunathan

IPC分类号： H01L29/40 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/10 ,  H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

摘要： Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.

公开(公告)号：US10403752B2

公开(公告)日：2019-09-03

申请号：US15525183

申请日：2014-12-22

申请人： Intel Corporation

发明人： Karthik Jambunathan ,  Glenn A. Glass ,  Chandra S. Mohapatra ,  Anand S. Murthy ,  Stephen M. Cea ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

摘要： An embodiment includes an apparatus comprising: a fin structure on a substrate, the fin structure including fin top and bottom portions, a channel including a majority carrier, and an epitaxial (EPI) layer; an insulation layer including insulation layer top and bottom portions adjacent the fin top and bottom portions; wherein (a) the EPI layer comprises one or more of group IV and lll-V materials, (b) the fin bottom portion includes a fin bottom portion concentration of dopants of opposite polarity to the majority carrier, (c) the fin top portion includes a fin top portion concentration of the dopants less than the fin bottom portion concentration, (d) the insulation layer bottom portion includes an insulation layer bottom portion concentration of the dopants, and (e) the insulation layer top portion includes an insulation top layer portion concentration greater than the insulation bottom portion concentration. Other embodiments are described herein.

公开(公告)号：US20190221641A1

公开(公告)日：2019-07-18

申请号：US16327034

申请日：2016-09-30

申请人： INTEL CORPORATION

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Nabil G. Mistkawi ,  Karthik Jambunathan ,  Tahir Ghani

IPC分类号： H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/02527 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/06 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785

摘要： Techniques are disclosed for forming nanowire transistors employing carbon-based layers. Carbon is added to the sacrificial layers and/or non-sacrificial layers of a multilayer stack forming one or more nanowires in the transistor channel region. Such carbon-based layers reduce or prevent diffusion and intermixing of the sacrificial and non-sacrificial portions of the multilayer stack. The reduction of diffusion/intermixing can allow for the originally formed layers to effectively maintain their original thicknesses, thereby enabling the formation of relatively more nanowires for a given channel region height because of the more accurate processing scheme. The techniques can be used to benefit group IV semiconductor material nanowire devices (e.g., devices including Si, Ge, and/or SiGe) and can also assist with the selective etch processing used to form the nanowires. The carbon concentration of the sacrificial and/or non-sacrificial layers can be adjusted to facilitate etch process to liberate nanowires in the channel region.

公开(公告)号：US20180358436A1

公开(公告)日：2018-12-13

申请号：US15778724

申请日：2015-12-24

申请人： Intel Corporation

发明人： Karthik Jambunathan ,  Glenn Glass ,  Anand Murthy ,  Jun Sung Kang ,  Seiyon Kim

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78696

摘要： Methods of forming self-aligned nanowire spacer structures are described. An embodiment includes forming a channel structure comprising a first nanowire and a second nanowire. Source/drain structures are formed adjacent the channel structure, wherein a liner material is disposed on at least a portion of the sidewalls of the source/drain structures. A nanowire spacer structure is formed between the first and second nanowires, wherein the nanowire spacer comprises an oxidized portion of the liner.

公开(公告)号：US11757037B2

公开(公告)日：2023-09-12

申请号：US17569643

申请日：2022-01-06

申请人： Intel Corporation

发明人： Karthik Jambunathan ,  Biswajeet Guha ,  Anupama Bowonder ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423

CPC分类号： H01L29/7846 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/42392

摘要： Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

公开(公告)号：US11735670B2

公开(公告)日：2023-08-22

申请号：US17497864

申请日：2021-10-08

申请人： Intel Corporation

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/161 ,  H01L27/088 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

摘要： Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.