公开(公告)号：US11189730B2

公开(公告)日：2021-11-30

申请号：US16649716

申请日：2017-12-26

申请人： INTEL CORPORATION

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/161 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

摘要： Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

公开(公告)号：US20200219774A1

公开(公告)日：2020-07-09

申请号：US16640470

申请日：2017-09-22

申请人： Intel Corporation

发明人： Karthik Jambunathan ,  Cory C. Bomberger ,  Anand S. Murthy

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

摘要： Techniques are described for forming strained fins for co-integrated n-MOS and p-MOS devices that include one or more defect trapping layers that prevent defects from migrating into channel regions of the various co-integrated n-MOS and p-MOS devices. A defect trapping layer can include one or more patterned dielectric layers that define aspect ratio trapping trenches. An alternative defect trapping layer can include a superlattice structure of alternating, epitaxially mismatched materials that provides an energetic barrier to the migration of defect. Regardless, the defect trapping layer can prevent dislocations, stacking faults, and other crystallographic defects present in a relaxed silicon germanium layer from migrating into strained n-MOS and p-MOS channel regions grown thereon.

公开(公告)号：US11699756B2

公开(公告)日：2023-07-11

申请号：US17541199

申请日：2021-12-02

申请人： Intel Corporation

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC分类号： H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/7846 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/42364

摘要： Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

公开(公告)号：US20230207560A1

公开(公告)日：2023-06-29

申请号：US17561244

申请日：2021-12-23

申请人： Intel Corporation

发明人： Cory C. Bomberger ,  Nicholas Minutillo ,  Ryan Cory Haislmaier ,  Yulia Tolstova ,  Yoon Jung Chang ,  Tahir Ghani ,  Szuya S. Liao ,  Anand Murthy ,  Pratik Patel

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/66 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/66795 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/823412

摘要： An integrated circuit (IC) structure, an IC device, an IC device assembly, and a method of forming the same. The IC structure includes a transistor device on a substrate comprising: a gate structure including a metal, the gate structure on a channel structure; a source structure in a first trench at a first side of the gate structure; a drain structure in a second trench at a second side of the gate structure; a capping layer on individual ones of the source structure and of the drain structure. The capping layer comprising a semiconductor material of a same group as a semiconductor material of a corresponding one of the source structure or of the drain structure, wherein an isotope of a p-type dopant in the capping layer represents an atomic percentage of at least about 95% of a p-type isotope content of the capping layer; and metal contact structures coupled to respective ones of the source structure and of the drain structure.

公开(公告)号：US11575005B2

公开(公告)日：2023-02-07

申请号：US15942252

申请日：2018-03-30

申请人： INTEL CORPORATION

发明人： Seung Hoon Sung ,  Dipanjan Basu ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Siddharth Chouksey ,  Cory C. Bomberger ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

摘要： An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.

公开(公告)号：US11482457B2

公开(公告)日：2022-10-25

申请号：US16640470

申请日：2017-09-22

申请人： Intel Corporation

发明人： Karthik Jambunathan ,  Cory C. Bomberger ,  Anand S. Murthy

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

摘要： Techniques are described for forming strained fins for co-integrated n-MOS and p-MOS devices that include one or more defect trapping layers that prevent defects from migrating into channel regions of the various co-integrated n-MOS and p-MOS devices. A defect trapping layer can include one or more patterned dielectric layers that define aspect ratio trapping trenches. An alternative defect trapping layer can include a superlattice structure of alternating, epitaxially mismatched materials that provides an energetic barrier to the migration of defect. Regardless, the defect trapping layer can prevent dislocations, stacking faults, and other crystallographic defects present in a relaxed silicon germanium layer from migrating into strained n-MOS and p-MOS channel regions grown thereon.

公开(公告)号：US20190305085A1

公开(公告)日：2019-10-03

申请号：US15942252

申请日：2018-03-30

申请人： INTEL CORPORATION

发明人： Seung Hoon Sung ,  Dipanjan Basu ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Siddharth Chouksey ,  Cory C. Bomberger ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

摘要： An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.

公开(公告)号：US20230207317A1

公开(公告)日：2023-06-29

申请号：US17560641

申请日：2021-12-23

申请人： Intel Corporation

发明人： Cory C. Bomberger ,  Karthik Jambunathan ,  Anand Murthy ,  Ju Nam ,  Tahir Ghani

IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L21/02694 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/1054 ,  H01L29/785

摘要： In one embodiment, an integrated circuit includes a substrate, a buffer layer, a source region, a drain region, a channel region, and a gate structure. The substrate includes silicon. The buffer layer is above the substrate and includes a semiconductor material having defects near an interface with the substrate. The buffer layer also includes ions implanted among the defects. The source region and drain region are above the buffer layer, and the channel region is above the buffer layer and between the source and drain regions. The gate structure above the channel region.

公开(公告)号：US11430787B2

公开(公告)日：2022-08-30

申请号：US16639024

申请日：2017-09-26

申请人： Intel Corporation

发明人： Karthik Jambunathan ,  Scott J. Maddox ,  Cory C. Bomberger ,  Anand S. Murthy

IPC分类号： H01L27/08 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285

摘要： Techniques for forming contacts comprising at least one crystal on source and drain (S/D) regions of semiconductor devices are described. Crystalline S/D contacts can be formed so as to conform to some or all of the top and side surfaces of the S/D regions. Crystalline S/D contacts of the present disclosure are formed by selectively depositing precursor on an exposed portion of one or more S/D regions. The precursor are then reacted in situ on the exposed portion of the S/D region. This reaction forms the conductive, crystalline S/D contact that conforms to the surface of the S/D regions.

公开(公告)号：US11222977B2

公开(公告)日：2022-01-11

申请号：US16641022

申请日：2017-09-26

申请人： Intel Corporation

发明人： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC分类号： H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423

摘要： Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.