FinFET source-drain merged by silicide-based material
    14.
    发明授权
    FinFET source-drain merged by silicide-based material 有权
    FinFET源极 - 漏极由硅化物材料合并

    公开(公告)号:US09595524B2

    公开(公告)日:2017-03-14

    申请号:US14561632

    申请日:2014-12-05

    摘要: A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a top portion of a silicon cap layer located in direct contact with a first diamond shaped epitaxial layer surrounding a first fin and a second diamond shaped epitaxial layer surrounding a second fin. The metal layer extends from the top portion of the silicon cap layer in direct contact with the first diamond shaped epitaxial layer to the top portion of the silicon cap layer in direct contact with the second diamond shaped epitaxial layer. The conducted laser-based anneal treatment forms a silicide layer, a portion of the silicide layer between the first and the second diamond shaped epitaxial layers is substantially thicker than a portion of the silicide layer in contact with the first and the second diamond shaped epitaxial layers.

    摘要翻译: 一种方法包括对位于与包围第一鳍片的第一菱形外延层直接接触的硅帽层顶部直接接触的金属层上进行基于激光的退火处理,第二菱形外延 围绕第二鳍的层。 金属层从第一金刚石外延层的直接接触的硅帽层的顶部延伸到硅帽层的顶部,与第二菱形外延层直接接触。 所进行的基于激光的退火处理形成硅化物层,第一和第二菱形外延层之间的硅化物层的一部分基本上比与第一和第二菱形外延层接触的硅化物层的部分厚 。

    FinFET source-drain merged by silicide-based material
    15.
    发明授权
    FinFET source-drain merged by silicide-based material 有权
    FinFET源极 - 漏极由硅化物材料合并

    公开(公告)号:US09543167B2

    公开(公告)日:2017-01-10

    申请号:US14331267

    申请日:2014-07-15

    摘要: A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a first diamond shaped epitaxial layer surrounding a first fin and a second diamond shaped epitaxial layer surrounding a second fin, the metal layer extends from the first diamond shaped epitaxial layer to the second diamond shaped epitaxial layer, the laser-based anneal treatment forms a silicide layer, a portion of the silicide layer between the first and the second diamond shaped epitaxial layers is substantially thicker than a portion of the silicide layer in contact with the first and the second diamond shaped epitaxial layers, and the silicide layer takes on a crystal orientation of the first and the second epitaxial layers.

    摘要翻译: 一种方法包括对围绕第一鳍片的第一菱形外延层和围绕第二鳍片的第二菱形外延层直接接触的金属层进行基于激光的退火处理,金属层从第一 金刚石外延层到第二菱形外延层,基于激光的退火处理形成硅化物层,第一和第二菱形外延层之间的硅化物层的一部分基本上比硅化物层的一部分厚 与第一和第二菱形外延层接触,硅化物层承受第一和第二外延层的晶体取向。

    Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening
    16.
    发明授权
    Blanket short channel roll-up implant with non-angled long channel compensating implant through patterned opening 有权
    毯子短通道卷起植入物,具有通过图案化开口的非角度长通道补偿植入物

    公开(公告)号:US09478615B2

    公开(公告)日:2016-10-25

    申请号:US14493749

    申请日:2014-09-23

    摘要: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

    摘要翻译: 一种形成将衬底植入衬底的结构的方法,在衬底上图案掩模(具有暴露衬底的沟道区的至少一个开口),并在掩模上形成共形电介质层并使开口 。 保形介电层覆盖衬底的沟道区。 该方法还在保形电介质层上形成共形栅极金属层,通过共形栅极金属层和共形绝缘层将补偿注入植入衬底的沟道区,并在共形栅极金属层上形成栅极导体。 此外,该方法去除掩模以在衬底上留下栅极堆叠,在栅极堆叠上形成侧壁间隔物,然后在衬底中部分地在侧壁间隔物下方形成源极/漏极区域。

    INTERCONNECTS FOR VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS

    公开(公告)号:US20180006023A1

    公开(公告)日:2018-01-04

    申请号:US15198044

    申请日:2016-06-30

    摘要: Structures and fabrication methods for vertical-transport field-effect transistors. The structure includes a vertical-transport field-effect transistor having a source/drain region located in a semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin. The structure further includes an interconnect located in a trench defined in the semiconductor layer. The interconnect is coupled with the source/drain region or the gate electrode of the vertical-transport field-effect transistor, and may be used to couple the source/drain region or the gate electrode of the vertical-transport field-effect transistor with a source/drain region or a gate electrode of another vertical-transport field-effect transistor.

    INTEGRATED CIRCUIT STRUCTURE WITH METHODS OF ELECTRICALLY CONNECTING SAME
    19.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE WITH METHODS OF ELECTRICALLY CONNECTING SAME 有权
    集成电路结构与电连接方法

    公开(公告)号:US20170005101A1

    公开(公告)日:2017-01-05

    申请号:US14754958

    申请日:2015-06-30

    摘要: Embodiments of the present disclosure provide an integrated circuit (IC) structure and methods of electrically connecting multiple IC structures. An IC structure according to embodiments of the present disclosure can include: a first conductive region; a second conductive region laterally separated from the first conductive region; a first vertically-oriented semiconductor fin formed over and contacting the first conductive region; a second vertically-oriented semiconductor fin formed over and contacting the second conductive region; and a first gate contacting each of the first vertically-oriented semiconductor fin and the second conductive region, wherein the first gate includes: a substantially horizontal section contacting the first vertically-oriented semiconductor fin, and a substantially vertical section contacting the second conductive region.

    摘要翻译: 本公开的实施例提供集成电路(IC)结构和电连接多个IC结构的方法。 根据本公开的实施例的IC结构可以包括:第一导电区域; 与所述第一导电区域横向分离的第二导电区域; 在所述第一导电区域上形成并接触所述第一垂直取向的半导体鳍片; 形成在第二导电区域上并与第二导电区域接触的第二垂直取向半导体鳍片; 以及与所述第一垂直取向的半导体鳍片和所述第二导电区域中的每一个接触的第一栅极,其中所述第一栅极包括:接触所述第一垂直取向的半导体鳍片的基本水平的部分和与所述第二导电区域接触的基本垂直的部分。

    Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s)
    20.
    发明授权
    Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s) 有权
    具有低电阻源极/漏极接触的场效应晶体管的半导体结构

    公开(公告)号:US09496394B2

    公开(公告)日:2016-11-15

    申请号:US14523083

    申请日:2014-10-24

    摘要: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.

    摘要翻译: 公开了包括具有低电阻源极/漏极接触和可选地低栅极 - 源极/漏极接触电容的场效应晶体管(FET)的半导体结构。 该结构包括半导体本体,并包含在其中,第一和第二源极/漏极区域和沟道区域。 第一栅极在沟道区域处与半导体本体相邻,并且第二非功能栅极与半导体本体相邻,使得第二源极/漏极区域位于第一和第二栅极之间。 第一和第二源极/漏极触点分别位于第一和源极/漏极区域上。 第二源极/漏极触点比第一源极/漏极触点更宽,因此具有较低的电阻。 此外,第一和第二源极/漏极接触件相对于第一栅极的间隔可以使得第一栅极至第二源极/漏极接触电容等于或小于第一栅极至第一源极/漏极接触 电容。 还公开了相关的形成方法。