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59 条记录 (耗时 0.02 秒)

    Manufacturing of memory array and periphery
    11.
    发明授权
    Manufacturing of memory array and periphery 有权
    内存阵列和周边的制造

    公开(公告)号：US07482231B2

    公开(公告)日：2009-01-27

    申请号：US11529067

    申请日：2006-09-28

    申请人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    发明人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    IPC分类号： H01L21/8239

    CPC分类号： H01L29/4983 ,  H01L21/28282 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

    摘要： Method of manufacturing a semiconductor chip. An array region gate stack is formed on an array region of a substrate and a periphery region gate stack is formed on a periphery region of a substrate. A first dielectric material, a charge-storing material, and a second dielectric material are deposited over the substrate. Portions of the first dielectric material, the charge-storing material, and the second dielectric material are removed to form storage structures on the array region gate stack and on the periphery region gate stack. The storage structures have a generally L-shaped cross-section. A first source/drain region is formed in the array region well. A third dielectric material and a spacer material are deposited over the substrate. Portions of the third dielectric material and the spacer material are removed to form spacers. A second source/drain region is formed in the periphery region well.

    摘要翻译： 制造半导体芯片的方法 在基板的阵列区域上形成阵列区域栅极叠层，并且在基板的周边区域上形成周边区域栅叠层。 在衬底上沉积第一介电材料，电荷存储材料和第二介电材料。 去除第一介电材料的部分，电荷存储材料和第二介电材料，以在阵列区域栅极叠层和周边区域栅叠层上形成存储结构。 存储结构具有大致L形的横截面。 在阵列区域中形成第一源极/漏极区域。 在衬底上沉积第三介电材料和间隔物材料。 去除第三电介质材料和间隔物材料的部分以形成间隔物。 在周边区域中形成第二源极/漏极区域。

    Sidewall SONOS gate structure with dual-thickness oxide and method of fabricating the same
    12.
    发明申请
    Sidewall SONOS gate structure with dual-thickness oxide and method of fabricating the same 审中-公开
    侧壁SONOS门结构与双层氧化物及其制造方法相同

    公开(公告)号：US20070075385A1

    公开(公告)日：2007-04-05

    申请号：US11243165

    申请日：2005-10-04

    申请人： Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    发明人： Tzyh-Cheang Lee ,  Jiunn-Ren Hwang ,  Tsung-Lin Lee

    IPC分类号： H01L29/94 ,  H01L29/76

    CPC分类号： H01L29/7923 ,  H01L29/40117 ,  H01L29/4234

    摘要： A SONOS gate structure has an oxide structure on a substrate having gate pattern thereon. The oxide structure has a relatively thinner oxide portion on the substrate for keeping good program/erase efficiency, and a relatively thicker oxide portion on sidewalls of the gate pattern for inhibiting gate disturb. Trapping dielectric spacers are on formed the oxide structure laterally adjacent to said sidewalls of said gate pattern respectively.

    摘要翻译： SONOS栅极结构在其上具有栅极图案的衬底上具有氧化物结构。 氧化物结构在衬底上具有相对较薄的氧化物部分，用于保持良好的编程/擦除效率，并且在用于抑制栅极干扰的栅极图案的侧壁上的相对较厚的氧化物部分。 捕获电介质间隔物分别形成在与所述栅极图案的所述侧壁相邻的氧化物结构上。

    Semiconductor structure and method for forming thereof
    14.
    发明申请
    Semiconductor structure and method for forming thereof 审中-公开
    半导体结构及其形成方法

    公开(公告)号：US20060286730A1

    公开(公告)日：2006-12-21

    申请号：US11154377

    申请日：2005-06-15

    申请人： Yi-Cheng Liu (Alex Liu) ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau

    发明人： Yi-Cheng Liu (Alex Liu) ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau

    IPC分类号： H01L21/8234 ,  H01L21/336

    CPC分类号： H01L29/7848 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

    摘要： A semiconductor structure and a method for forming the semiconductor structure are provided. The method for forming a semiconductor structure of the present invention may include the following steps. First, a substrate is provided, wherein a gate is formed over the substrate, and a plurality of offspacers are formed over a sidewall of the gate. Then, a source/drain trench is formed in the substrate at two sides of the gate respectively. Next, an outermost offspacer of the offspacers is removed to expose a flat surface on a surface of the substrate. Thereafter, the source/drain trenches are filled to form a source/drain region. Then, a lightly doped drain (LDD) region is formed in a portion of the substrate under the flat surface.

    摘要翻译： 提供半导体结构和形成半导体结构的方法。 本发明的半导体结构的形成方法可以包括以下步骤。 首先，提供衬底，其中在衬底上形成栅极，并且在栅极的侧壁上方形成多个脱离层。 然后，在栅极的两侧分别在衬底中形成源极/漏极沟槽。 接下来，除去离子的最外层的隔离物以露出基底表面上的平坦表面。 此后，填充源极/漏极沟槽以形成源极/漏极区域。 然后，在平坦表面下的基板的一部分中形成轻掺杂漏极（LDD）区域。

    Method of correcting a mask layout
    16.
    发明授权
    Method of correcting a mask layout 有权
    校正掩模布局的方法

    公开(公告)号：US06974650B2

    公开(公告)日：2005-12-13

    申请号：US10063779

    申请日：2002-05-12

    申请人： Kay Ming Lee ,  Cheng-Wen Fan ,  Jiunn-Ren Hwang ,  Chih-Chiang Liu

    发明人： Kay Ming Lee ,  Cheng-Wen Fan ,  Jiunn-Ren Hwang ,  Chih-Chiang Liu

    IPC分类号： G03F1/00 ,  G03F1/36 ,  G03F9/00

    CPC分类号： G03F1/36

    摘要： A method of correcting a mask layout is provided. The mask layout includes a plurality of element patterns. An inspection program is executed to classify the element patterns of the mask layout into a plurality of element pattern types according to a pattern density of the element patterns. Following this, each of the element pattern types is corrected so as to prevent a plasma micro-loading effect.

    摘要翻译： 提供了一种校正掩模布局的方法。 掩模布局包括多个元素图案。 执行检查程序，以根据元件图案的图案密度将掩模布局的元素图案分类为多个元素图案类型。 此后，校正每个元件图案类型以防止等离子体微负载效应。

    Structure of a trapezoid-triple-gate FET
    17.
    发明授权
    Structure of a trapezoid-triple-gate FET 有权
    梯形三栅极FET的结构

    公开(公告)号：US06853031B2

    公开(公告)日：2005-02-08

    申请号：US10417167

    申请日：2003-04-17

    申请人： Wen-Shiang Liao ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau

    发明人： Wen-Shiang Liao ,  Jiunn-Ren Hwang ,  Wei-Tsun Shiau

    IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/66787 ,  H01L29/0657 ,  H01L29/1037 ,  H01L29/42376

    摘要： A structure of a Trapezoid-Triple-Gate Field Effect Transistor (FET) includes a plurality of trapezoid pillars being transversely formed on an crystalline substrate or Silicon-On-Insulator (SOI) wafer. The trapezoid pillars can juxtapose with both ends connected each other. Each trapezoid pillar has a source, a channel region, and a drain aligned in longitudinal direction and a gate latitudinally superposes the channel region of the trapezoid pillar. The triple gate field effect transistor comprises a dielectric layer formed between the channel region and the conductive gate structure.

    摘要翻译： 梯形三栅场效应晶体管（FET）的结构包括在晶体衬底或绝缘体上硅晶片上横向形成的多个梯形柱。 梯形柱可以并置，两端相互连接。 每个梯形柱具有在纵向方向上排列的源极，沟道区和漏极，栅极横向叠加梯形柱的沟道区域。 三栅场效应晶体管包括形成在沟道区和导电栅结构之间的电介质层。

    Optical proximity correction of pattern on photoresist through spacing of sub patterns
    19.
    发明授权
    Optical proximity correction of pattern on photoresist through spacing of sub patterns 有权
    通过子图案的间隔对光致抗蚀剂上的图案进行光学邻近校正

    公开(公告)号：US06613485B2

    公开(公告)日：2003-09-02

    申请号：US10045432

    申请日：2002-01-11

    申请人： Jui-Tsen Huang ,  Jiunn-Ren Hwang

    发明人： Jui-Tsen Huang ,  Jiunn-Ren Hwang

    IPC分类号： G03F900

    CPC分类号： G03F1/36 ,  Y10S430/143

    摘要： An optical proximity correction method for rectifying pattern on photoresist. Line pattern of integrated circuit is divided into L-shape regions or T-shaped regions. The L-shaped or T-shaped regions are further dissected into rectangular patches. Area of each rectangular patch is suitably reduced and reproduced onto a photomask. The photomask is used to form a corrected photoresist pattern.

    摘要翻译： 一种用于在光致抗蚀剂上整流图案的光学邻近校正方法。 集成电路的线路图案分为L形区域或T形区域。 L形或T形区域进一步分解成矩形斑块。 每个矩形贴片的面积被适当地减小并再现到光掩模上。 光掩模用于形成校正的光致抗蚀剂图案。