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1.发明申请公开(公告)号：US20120045712A1
公开(公告)日：2012-02-23
申请号：US12858159
申请日：2010-08-17
申请人： Ching-Hsu CHANG , Hung-Chun WANG , Boren LUO , Wen-Chun HUANG , Ru-Gun LIU
发明人： Ching-Hsu CHANG , Hung-Chun WANG , Boren LUO , Wen-Chun HUANG , Ru-Gun LIU
摘要： Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A planarizing process is provided to remove the absorber layer above the top surface of the hard mask layer and form an absorber in the opening, wherein the absorber is substantially co-planar with the top surface of the hard mask layer.
摘要翻译： 提供EUV光掩模的实施例和形成EUV光掩模的方法。 该方法包括提供衬底，反射层，覆盖层，硬掩模层，以及在其中形成开口。 然后将吸收层填充在硬掩模层的开口中和上表面上。 提供平面化处理以去除硬掩模层的顶表面之上的吸收层，并在开口中形成吸收体，其中吸收体与硬掩模层的顶表面基本上共面。
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2.发明授权公开(公告)号：US08764995B2
公开(公告)日：2014-07-01
申请号：US12858159
申请日：2010-08-17
申请人： Ching-Hsu Chang , Hung-Chun Wang , Boren Luo , Wen-Chun Huang , Ru-Gun Liu
发明人： Ching-Hsu Chang , Hung-Chun Wang , Boren Luo , Wen-Chun Huang , Ru-Gun Liu
摘要： Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A planarizing process is provided to remove the absorber layer above the top surface of the hard mask layer and form an absorber in the opening, wherein the absorber is substantially co-planar with the top surface of the hard mask layer.
摘要翻译： 提供EUV光掩模的实施例和形成EUV光掩模的方法。 该方法包括提供衬底，反射层，覆盖层，硬掩模层，以及在其中形成开口。 然后将吸收层填充在硬掩模层的开口中和上表面上。 提供平面化处理以去除硬掩模层的顶表面之上的吸收层，并在开口中形成吸收体，其中吸收体与硬掩模层的顶表面基本上共面。
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公开(公告)号：US20130258304A1
公开(公告)日：2013-10-03
申请号：US13437145
申请日：2012-04-02
CPC分类号： G03F1/22 , G03F1/70 , G03F7/70066 , G03F7/70283 , G03F7/70433
摘要： The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.
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公开(公告)号：US06589881B2
公开(公告)日：2003-07-08
申请号：US09997339
申请日：2001-11-27
IPC分类号： H01L21302
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/76813
摘要： A method of forming a dual damascene structure. A substrate having a conductive layer thereon is provided. A passivation layer, a first dielectric layer, an etching stop layer, a second dielectric layer and cap layer serving as a base anti-reflection coating are sequentially formed over the substrate. The cap layer and the second dielectric layer are patterned to form a first opening that exposes a portion of the etching stop layer. A patterned negative photoresist layer having a second opening therein is formed above the cap layer. The cap layer exposed by the second opening and the second dielectric layer exposed by the first opening are removed. Thereafter, the second dielectric layer exposed by the second opening is removed to form a trench and the first dielectric layer exposed by the first opening is removed to form a via opening. The passivation layer exposed by via opening and then the negative photoresist layer is removed. A conformal barrier layer and a conductive layer are sequentially formed over the trench and the via opening with the conductive layer, completely filling the trench and the via opening.
摘要翻译： 形成双镶嵌结构的方法。 提供其上具有导电层的基板。 在衬底上顺序形成钝化层，第一介电层，蚀刻停止层，第二电介质层和用作基底防反射涂层的覆盖层。 将盖层和第二介电层图案化以形成暴露蚀刻停止层的一部分的第一开口。 在其上方形成了具有第二开口的图案化的负性光致抗蚀剂层。 除去由第二开口暴露的盖层和由第一开口露出的第二介质层。 此后，除去由第二开口露出的第二电介质层以形成沟槽，并且去除由第一开口暴露的第一电介质层以形成通孔。 去除通过开口暴露的钝化层，然后去除负的光致抗蚀剂层。 在沟槽和通孔开口上依次形成保形阻挡层和导电层，导电层完全填充沟槽和通孔。
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公开(公告)号：US06391757B1
公开(公告)日：2002-05-21
申请号：US09875508
申请日：2001-06-06
IPC分类号： H01L2144
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031
摘要： A dual damascene process involves forming a first passivation layer, a first dielectric layer and a second passivation layer on a substrate of a semiconductor wafer. A first lithography and etching process is performed to form at least one via hole in the second passivation layer and the first dielectric layer. Thereafter, a second dielectric layer and a third passivation layer are formed on the surface of the semiconductor wafer followed by performing a second lithography and etching process to form at least one trench in the third passivation layer and the second dielectric layer. The trench and the via hole together construct a dual damascene structure. Finally, a barrier layer and a metal layer are formed on the surface of the semiconductor wafer, and a chemical-mechanical-polishing (CMP) process is performed to complete the dual damascene process.
摘要翻译： 双镶嵌工艺包括在半导体晶片的衬底上形成第一钝化层，第一介电层和第二钝化层。 执行第一光刻和蚀刻工艺以在第二钝化层和第一介电层中形成至少一个通孔。 此后，在半导体晶片的表面上形成第二电介质层和第三钝化层，随后进行第二光刻和蚀刻工艺，以在第三钝化层和第二介电层中形成至少一个沟槽。 沟槽和通孔一起构成双镶嵌结构。 最后，在半导体晶片的表面上形成阻挡层和金属层，进行化学机械抛光（CMP）工艺以完成双镶嵌工艺。
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公开(公告)号：US09091930B2
公开(公告)日：2015-07-28
申请号：US13437145
申请日：2012-04-02
CPC分类号： G03F1/22 , G03F1/70 , G03F7/70066 , G03F7/70283 , G03F7/70433
摘要： The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.
摘要翻译： 本公开提供了一种半导体光刻系统。 光刻系统包括投影光学部件。 投影光学部件包括弯曲孔。 光刻系统包括位于投影光学部件上的光掩模。 光掩模包含多个细长半导体图案。 半导体图案各自指向基本上垂直于投影光学部件的弯曲孔径的方向。 本公开还提供了一种方法。 该方法包括接收半导体器件的设计布局。 设计布局包含多个沿给定方向定向的半导体图案。 该方法包括将设计布局转换为蒙版布局。 作为其各自位置的函数，掩模布局中的半导体图案被定向在多个不同的方向上。
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公开(公告)号：US06839126B2
公开(公告)日：2005-01-04
申请号：US10033891
申请日：2002-01-03
CPC分类号： G03F7/70141 , G03F7/70425 , G03F7/70466
摘要： A photolithography process with multiple exposures is provided. A photomask is placed and aligned above a wafer having a photoresist formed thereon at a predetermined distance. Multiple exposures are sequentially performed on the photoresist through the photomask. Each of the multiple exposures is provided with a respective illuminating setting that is optimized for one duty ratio of the photomask. Thereby, an optimum through-pitch performance for pattern transfer from the photomask unto the photoresist is obtained. Then, a development is performed on the photoresist.
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