公开(公告)号：US09671685B2

公开(公告)日：2017-06-06

申请号：US12976646

申请日：2010-12-22

申请人： Chin-Hsiang Lin ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Chiang Tu ,  Chun-Jen Chen ,  Rick Lai

发明人： Chin-Hsiang Lin ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Chiang Tu ,  Chun-Jen Chen ,  Rick Lai

IPC分类号： G06F17/50 ,  G03F1/72 ,  G03F1/86

CPC分类号： G03F1/72 ,  G03F1/86

摘要： The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired.

公开(公告)号：US08903532B2

公开(公告)日：2014-12-02

申请号：US13429921

申请日：2012-03-26

申请人： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

发明人： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

IPC分类号： H01L31/18

CPC分类号： G03F7/30 ,  G03F7/16 ,  G03F7/70991 ,  H01L21/67225 ,  H01L21/67745

摘要： The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

摘要翻译： 本公开涉及一种用于半导体工件加工的平版印刷工具装置。 光刻工具装置将光刻工具组合成簇，并且将半导体工件在第一簇中的第一类型的多个光刻工具之间选择性地传输到第二簇中的第二类型的光刻工具。 通过转移组件实现选择性转移，转移组件耦合到识别第一类型的光刻工具中产生的缺陷的缺陷扫描工具。 所公开的平版印刷工具装置还利用共同的结构元件，例如壳体组件和诸如气体和化学品的共享功能元件。 光刻工具装置可以包括被配置成提供这些各种部件的模块化的烘烤，涂覆，曝光和显影单元，以便为给定的光刻制造工艺优化产量和效率。

公开(公告)号：US08592287B2

公开(公告)日：2013-11-26

申请号：US13196200

申请日：2011-08-02

申请人： Chi-Yuan Shih ,  I-Hsiung Huang ,  Heng-Hsin Liu

发明人： Chi-Yuan Shih ,  I-Hsiung Huang ,  Heng-Hsin Liu

IPC分类号： H01L21/00

CPC分类号： G01N23/04 ,  G01N2223/418 ,  G01N2223/611 ,  G03F7/70633

摘要： A method comprises providing a semiconductor substrate having a first layer and a second layer above the first layer. The first layer haw a plurality of first patterns, vias or contacts. The second layer has second patterns corresponding to the first patterns, vias or contacts. The second patterns have a plurality of in-plane offsets relative to the corresponding first patterns, vias or contacts. A scanning electron microscope is used to measure line edge roughness (LER) values of the second patterns. An overlay error is calculated between the first and second layers based on the measured LER values.

摘要翻译： 一种方法包括提供在第一层上方具有第一层和第二层的半导体衬底。 第一层包含多个第一图案，通孔或接触。 第二层具有对应于第一图案，通孔或触点的第二图案。 第二图案相对于对应的第一图案，通孔或触点具有多个面内偏移。 扫描电子显微镜用于测量第二种图案的线条粗糙度（LER）值。 基于测量的LER值，在第一层和第二层之间计算覆盖误差。

公开(公告)号：US20130032712A1

公开(公告)日：2013-02-07

申请号：US13196200

申请日：2011-08-02

申请人： Chi-Yuan SHIH ,  I-Hsiung HUANG ,  Heng-Hsin LIU

发明人： Chi-Yuan SHIH ,  I-Hsiung HUANG ,  Heng-Hsin LIU

IPC分类号： G01N23/00 ,  H01L23/544

CPC分类号： G01N23/04 ,  G01N2223/418 ,  G01N2223/611 ,  G03F7/70633

摘要： A method comprises providing a semiconductor substrate having a first layer and a second layer above the first layer. The first layer haw a plurality of first patterns, vias or contacts. The second layer has second patterns corresponding to the first patterns, vias or contacts. The second patterns have a plurality of in-plane offsets relative to the corresponding first patterns, vias or contacts. A scanning electron microscope is used to measure line edge roughness (LER) values of the second patterns. An overlay error is calculated between the first and second layers based on the measured LER values.

摘要翻译： 一种方法包括提供在第一层上方具有第一层和第二层的半导体衬底。 第一层包含多个第一图案，通孔或接触。 第二层具有对应于第一图案，通孔或触点的第二图案。 第二图案相对于对应的第一图案，通孔或触点具有多个面内偏移。 扫描电子显微镜用于测量第二种图案的线条粗糙度（LER）值。 基于测量的LER值，在第一层和第二层之间计算覆盖误差。

公开(公告)号：US08278762B2

公开(公告)日：2012-10-02

申请号：US12568027

申请日：2009-09-28

申请人： Ling-Chieh Lin ,  Chien-Fu Lee ,  I-Hsiung Huang

发明人： Ling-Chieh Lin ,  Chien-Fu Lee ,  I-Hsiung Huang

IPC分类号： H01L23/48

CPC分类号： G03F1/36

摘要： A method of manufacturing a photomask is described. The graphic data of the photomask are provided, and than an optical proximity correction is performed to the graphic data. A process rule check is then performed to the graphic data with the optical proximity correction. When at least one failed pattern not passing the process rule check is found in the graphic data, a repair procedure is performed only to the failed pattern so that the failed pattern can pass the process rule check. The patterns of the photomask are then formed according to the corrected and repaired graphic data.

摘要翻译： 描述了制造光掩模的方法。 提供光掩模的图形数据，并且对图形数据进行光学邻近校正。 然后使用光学邻近校正对图形数据执行处理规则检查。 当在图形数据中找到至少一个未通过过程规则检查的故障模式时，仅对故障模式执行修复过程，以使故障模式能够通过进程规则检查。 然后根据校正和修复的图形数据形成光掩模的图案。

公开(公告)号：US20110159410A1

公开(公告)日：2011-06-30

申请号：US12650985

申请日：2009-12-31

申请人： Chin-Hsiang Lin ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Chiang Tu ,  Chun-Jen Chen ,  Rick Lai

发明人： Chin-Hsiang Lin ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Chiang Tu ,  Chun-Jen Chen ,  Rick Lai

IPC分类号： G03F1/00 ,  G06F17/50

CPC分类号： G03F1/24 ,  G03F1/72 ,  G03F1/84

摘要： The present disclosure provides for many different embodiments. An exemplary method can include providing a blank mask and a design layout to be patterned on the blank mask, the design layout including a critical area; inspecting the blank mask for defects and generating a defect distribution map associated with the blank mask; mapping the defect distribution map to the design layout; performing a mask making process; and performing a mask defect repair process based on the mapping.

摘要翻译： 本公开提供了许多不同的实施例。 示例性方法可以包括提供空白掩模和要在空白掩模上图案化的设计布局，所述设计布局包括临界区域; 检查空白掩模的缺陷并产生与空白掩模相关联的缺陷分布图; 将缺陷分布图映射到设计布局; 进行面膜制作过程; 以及基于所述映射执行掩模缺陷修复处理。

公开(公告)号：US20080163892A1

公开(公告)日：2008-07-10

申请号：US11621002

申请日：2007-01-08

申请人： I-Hsiung Huang ,  Ling-Chieh Lin

发明人： I-Hsiung Huang ,  Ling-Chieh Lin

IPC分类号： B08B3/08 ,  C11D7/00 ,  B08B7/00

CPC分类号： C11D11/0047 ,  B08B3/08 ,  C11D17/049 ,  G03F7/70341 ,  G03F7/70925 ,  G03F7/70933 ,  G03F7/70983 ,  H01L21/6704

摘要： A method of an in situ cleaning of an objective lens of a semiconductor apparatus includes placing a cleaning wafer having a detergent layer on a scanning stage of the semiconductor apparatus. A cleaning composition in the detergent layer is dissolved by using an immersion liquid (water), so that the cleaning composition reacts with the contaminants on the objective lens. Thereafter, the objective lens is rinsed with another solvent.

摘要翻译： 半导体装置的物镜的原位清洁方法包括将具有洗涤剂层的清洁晶片放置在半导体装置的扫描台上。 通过使用浸没液（水）将洗涤剂层中的清洁组合物溶解，使得清洁组合物与物镜上的污染物反应。 此后，用另一溶剂冲洗物镜。

公开(公告)号：US06391757B1

公开(公告)日：2002-05-21

申请号：US09875508

申请日：2001-06-06

申请人： I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Yeong-Song Yen ,  Ching-Hsu Chang

发明人： I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Yeong-Song Yen ,  Ching-Hsu Chang

IPC分类号： H01L2144

CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L2221/1031

摘要： A dual damascene process involves forming a first passivation layer, a first dielectric layer and a second passivation layer on a substrate of a semiconductor wafer. A first lithography and etching process is performed to form at least one via hole in the second passivation layer and the first dielectric layer. Thereafter, a second dielectric layer and a third passivation layer are formed on the surface of the semiconductor wafer followed by performing a second lithography and etching process to form at least one trench in the third passivation layer and the second dielectric layer. The trench and the via hole together construct a dual damascene structure. Finally, a barrier layer and a metal layer are formed on the surface of the semiconductor wafer, and a chemical-mechanical-polishing (CMP) process is performed to complete the dual damascene process.

摘要翻译： 双镶嵌工艺包括在半导体晶片的衬底上形成第一钝化层，第一介电层和第二钝化层。 执行第一光刻和蚀刻工艺以在第二钝化层和第一介电层中形成至少一个通孔。 此后，在半导体晶片的表面上形成第二电介质层和第三钝化层，随后进行第二光刻和蚀刻工艺，以在第三钝化层和第二介电层中形成至少一个沟槽。 沟槽和通孔一起构成双镶嵌结构。 最后，在半导体晶片的表面上形成阻挡层和金属层，进行化学机械抛光（CMP）工艺以完成双镶嵌工艺。

公开(公告)号：US06337269B1

公开(公告)日：2002-01-08

申请号：US09885042

申请日：2001-06-21

申请人： I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Kuei-Chun Hung

发明人： I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Kuei-Chun Hung

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/76804 ,  H01L21/76813

摘要： The present invention fabricates a dual damascene structure. A passivation layer, a first dielectric layer, a second passivation layer, a second dielectric layer, a third passivation layer and a third dielectric layer are formed on the surface of the semiconductor wafer followed by etching the third dielectric layer to form a pattern of an upper trench of the dual damascene structure. Then the third passivation layer and the second dielectric layer are etched down to the surface of the second passivation layer so as to form a pattern of a via hole of the dual damascene structure. Thereafter, the third passivation layer and the second passivation layer not covered by the third dielectric layer and the second dielectric layer are removed. The third dielectric layer and the second passivation layer are used as hard masks to remove the second dielectric layer and the first dielectric layer until the surface of the first passivation layer. Finally, the second passivation layer and the first passivation layer not covered by the second dielectric layer and the first dielectric layer are removed to the surface of the conductive layer so completing the process of fabricating the dual damascene structure.

摘要翻译： 本发明制造双镶嵌结构。 在半导体晶片的表面上形成钝化层，第一介电层，第二钝化层，第二介电层，第三钝化层和第三介电层，然后蚀刻第三介电层，形成图案 双层镶嵌结构的上沟槽。 然后，将第三钝化层和第二介电层向下蚀刻到第二钝化层的表面，以形成双镶嵌结构的通孔的图案。 此后，除去未被第三电介质层和第二电介质层覆盖的第三钝化层和第二钝化层。 第三介电层和第二钝化层用作硬掩模以去除第二介电层和第一介电层直到第一钝化层的表面。 最后，将第二钝化层和未被第二介电层和第一介电层覆盖的第一钝化层除去到导电层的表面，从而完成制造双镶嵌结构的工艺。

公开(公告)号：US09128320B2

公开(公告)日：2015-09-08

申请号：US12546711

申请日：2009-08-25

申请人： Wen-Lung Chen ,  Chih-Jen Hu ,  Yue-Shih Jeng ,  I-Hsiung Huang ,  Po-Wei Wu ,  Yu-June Wu ,  Chih-Wen Chen ,  Meng-Chieh Tsai

发明人： Wen-Lung Chen ,  Chih-Jen Hu ,  Yue-Shih Jeng ,  I-Hsiung Huang ,  Po-Wei Wu ,  Yu-June Wu ,  Chih-Wen Chen ,  Meng-Chieh Tsai

IPC分类号： G02F1/1335 ,  G02B27/22

CPC分类号： G02F1/133526 ,  G02B27/2214

摘要： A three-dimensional display including a display and a micro-lens is provided. The display has a plurality of pixel units thereon, and each pixel unit has a pixel pitch i. The micro-lens is disposed at a side of the display, the micro-lens has a plurality of lens units thereon, and each lens unit has a lens pitch l. A right eye viewing zone and a left eye viewing zone are formed if an image displayed from the display passes though the micro-lens, wherein a distance between the center of the right eye viewing zone and the center of the left eye viewing zone is wz, and lens pitch l satisfies: 2 ⁢ i > l ≥ 2 ⁢ i × w z w z + i , wz is between 70 and 500 mm and i is between 0.1 and 500 μm.

摘要翻译： 提供了包括显示器和微透镜的三维显示器。 显示器上具有多个像素单元，并且每个像素单元具有像素间距i。 微透镜设置在显示器的一侧，微透镜在其上具有多个透镜单元，并且每个透镜单元具有透镜间距l。 如果从显示器显示的图像通过微透镜，则形成右眼观察区域和左眼观察区域，其中右眼观察区域的中心与左眼观察区域的中心之间的距离为wz ，透镜间距l满足：2i>l≥2i×wzwz + i，wz为70〜500mm，i为0.1〜500μm。