公开(公告)号：US06391757B1

公开(公告)日：2002-05-21

申请号：US09875508

申请日：2001-06-06

申请人： I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Yeong-Song Yen ,  Ching-Hsu Chang

发明人： I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Yeong-Song Yen ,  Ching-Hsu Chang

IPC分类号： H01L2144

CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L2221/1031

摘要： A dual damascene process involves forming a first passivation layer, a first dielectric layer and a second passivation layer on a substrate of a semiconductor wafer. A first lithography and etching process is performed to form at least one via hole in the second passivation layer and the first dielectric layer. Thereafter, a second dielectric layer and a third passivation layer are formed on the surface of the semiconductor wafer followed by performing a second lithography and etching process to form at least one trench in the third passivation layer and the second dielectric layer. The trench and the via hole together construct a dual damascene structure. Finally, a barrier layer and a metal layer are formed on the surface of the semiconductor wafer, and a chemical-mechanical-polishing (CMP) process is performed to complete the dual damascene process.

摘要翻译： 双镶嵌工艺包括在半导体晶片的衬底上形成第一钝化层，第一介电层和第二钝化层。 执行第一光刻和蚀刻工艺以在第二钝化层和第一介电层中形成至少一个通孔。 此后，在半导体晶片的表面上形成第二电介质层和第三钝化层，随后进行第二光刻和蚀刻工艺，以在第三钝化层和第二介电层中形成至少一个沟槽。 沟槽和通孔一起构成双镶嵌结构。 最后，在半导体晶片的表面上形成阻挡层和金属层，进行化学机械抛光（CMP）工艺以完成双镶嵌工艺。

公开(公告)号：US06839126B2

公开(公告)日：2005-01-04

申请号：US10033891

申请日：2002-01-03

申请人： Yeong-Song Yen ,  I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Kuei-Chun Hung ,  Ching-Hsu Chang

发明人： Yeong-Song Yen ,  I-Hsiung Huang ,  Jiunn-Ren Hwang ,  Kuei-Chun Hung ,  Ching-Hsu Chang

IPC分类号： G03F7/20 ,  G03B27/74 ,  G03B27/42 ,  G03B27/54

CPC分类号： G03F7/70141 ,  G03F7/70425 ,  G03F7/70466

摘要： A photolithography process with multiple exposures is provided. A photomask is placed and aligned above a wafer having a photoresist formed thereon at a predetermined distance. Multiple exposures are sequentially performed on the photoresist through the photomask. Each of the multiple exposures is provided with a respective illuminating setting that is optimized for one duty ratio of the photomask. Thereby, an optimum through-pitch performance for pattern transfer from the photomask unto the photoresist is obtained. Then, a development is performed on the photoresist.

公开(公告)号：US06833318B2

公开(公告)日：2004-12-21

申请号：US10065803

申请日：2002-11-20

申请人： Chun-Jen Weng ,  Juan-Yi Chen ,  Hong-Tsz Pan ,  Cedric Lee ,  Der-Yuan Wu ,  Jackson Lin ,  Yeong-Song Yen ,  Lawrence Lin ,  Ying-Chung Tseng

发明人： Chun-Jen Weng ,  Juan-Yi Chen ,  Hong-Tsz Pan ,  Cedric Lee ,  Der-Yuan Wu ,  Jackson Lin ,  Yeong-Song Yen ,  Lawrence Lin ,  Ying-Chung Tseng

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/31144

摘要： A gap-filling process is provided. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material is removed from the gap-filling material layer to expose the dielectric layer. A gap-filling material treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity.

摘要翻译： 提供间隙填充过程。 提供其上具有介电层的基板。 电介质层中有一个开口。 在电介质层和开口内部形成间隙填充材料层。 间隙填充材料的一部分从间隙填充材料层去除以暴露电介质层。 进行间隙填充材料层和电介质层的表面的间隙填充材料处理以使间隙填充材料层平坦化，从而在间隙填充材料上形成随后形成的底部抗反射涂层或材料层 层可以具有高度的平面度。